Self-Checking and Fault-Tolerant Digital Design (Hardcover)

Parag K. Lala

  • 出版商: Morgan Kaufmann
  • 出版日期: 2000-06-26
  • 售價: $3,730
  • 貴賓價: 9.5$3,544
  • 語言: 英文
  • 頁數: 400
  • 裝訂: Hardcover
  • ISBN: 0124343708
  • ISBN-13: 9780124343702
  • 下單後立即進貨 (約2~3週)



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With VLSI chip transistors getting smaller and smaller, today's digital systems are more complex than ever before. This increased complexity leads to more cross-talk, noise, and other sources of transient errors during normal operation. Traditional off-line testing strategies cannot guarantee detection of these transient faults. And with critical applications relying on faster, more powerful chips, fault-tolerant, self-checking mechanisms must be built in to assure reliable operation.

Self-Checking and Fault-Tolerant Digital Design deals extensively with self-checking design techniques and is the only book that emphasizes major techniques for hardware fault tolerance. Graduate students in VLSI design courses as well as practicing designers will appreciate this balanced treatment of the concepts and theory underlying fault tolerance along with the practical techniques used to create fault-tolerant systems.


  • Introduces reliability theory and the importance of maintainability
  • Presents coding and the construction of several error detecting and correcting codes
  • Discusses in depth, the available techniques for fail-safe design of combinational circuits
  • Details checker design techniques for detecting erroneous bits and encoding output of self-checking circuits
  • Demonstrates how to design self-checking sequential circuits, including a technique for fail-safe state machine design


Parag Lala is the Mullins Chair Professor at the University of Arkansas, where he teaches in the Department of Computer Science and Computer Engineering. He is well known for his research in the areas of VLSI system design and testing, self-checking (on-line testable) logic circuit design, field-programmable logic devices, fault-tolerant system design, and embryonics. Parag received his M.Sc. (Eng.) degree from King's College, London, and his Ph.D. from the City University of London. In 1998 he received his D.Sc. (Eng.) degree from the University of London. He is the author of Digital Circuit Testing and Testability.

Table of Contents:

Chapter 1 - Fundamentals of Reliability
Chapter 2 - Error Detecting and Correcting Codes
Chapter 3 - Self-Checking Combinational Logic Design
Chapter 4 - Self-Checking Checkers
Chapter 5 - Self-Checking Sequential Circuit Design
Chapter 6 - Fault-Tolerant Design
Markov Models

Related Titles:

Computer Architecture & Design