Hardware Design Verification: Simulation and Formal Method-Based Approaches (Hardcover)

William K. Lam

  • 出版商: Prentice Hall
  • 出版日期: 2005-03-13
  • 售價: $1,380
  • 貴賓價: 9.5$1,311
  • 語言: 英文
  • 頁數: 624
  • 裝訂: Hardcover
  • ISBN: 0131433474
  • ISBN-13: 9780131433472
  • 已絕版

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Table of Contents:

Preface xvii
Acknowledgments xxiii
About the Author xxv

Chapter 1 An Invitation to Design Verification 1

1.1 What Is Design Verification? 2

1.2 The Basic Verification Principle 4

1.3 Verification Methodology 8

1.4 Simulation-Based Verification versus Formal Verification 15

1.5 Limitations of Formal Verification 17

1.6 A Quick Overview of Verilog Scheduling and Execution Semantics 17

1.7 Summary 23

Chapter 2 Coding for Verification 25

2.1 Functional Correctness 27

2.2 Timing Correctness 39

2.3 Simulation Performance 44

2.4 Portability and Maintainability 52

2.5 "Synthesizability," "Debugability," and General Tool Compatibility 56

2.6 Cycle-Based Simulation 59

2.7 Hardware Simulation/Emulation 62

2.8 Two-State and Four-State Simulation 64

2.9 Design and Use of a Linter 66

2.10 Summary 67

2.11 Problems 67

Chapter 3 Simulator Architectures and Operations 73

3.1 The Compilers 74

3.2 The Simulators 79

3.3 Simulator Taxonomy and Comparison 108

3.4 Simulator Operations and Applications 112

3.5 Incremental Compilation 126

3.6 Summary 129

3.7 Problems 130

Chapter 4 Test Bench Organization and Design 137

4.1 Anatomy of a Test Bench and a Test Environment 137

4.2 Initialization Mechanism 142

4.3 Clock Generation and Synchronization 148

4.4 Stimulus Generation 155

4.5 Response Assessment 162

4.6 Verification Utility 183

4.7 Test Bench-to-Design Interface 195

4.8 Common Practical Techniques and Methodologies 196

4.9 Summary 204

4.10 Problems 204

Chapter 5 Test Scenarios, Assertions, and Coverage 211

5.1 Hierarchical Verification 214

5.2 Test Plan 217

5.3 Pseudorandom Test Generator 227

5.4 Assertions 232

5.5 SystemVerilog Assertions 248

5.6 Verification Coverage 259

5.7 Summary 279

5.8 Problems 280

Chapter 6 Debugging Process and Verification Cycle 287

6.1 Failure Capture, Scope Reduction, and Bug Tracking 288

6.2 Simulation Data Dumping 297

6.3 Isolation of Underlying Causes 300

6.4 Design Update and Maintenance: Revision Control 315

6.5 Regression, Release Mechanism, and Tape-out Criteria 318

6.6 Summary 321

6.7 Problems 322

Chapter 7 Formal Verification Preliminaries 331

7.1 Sets and Operations 332

7.2 Relation, Partition, Partially Ordered Set, and Lattice 334

7.3 Boolean Functions and Representations 342

7.4 Boolean Functional Operators 353

7.5 Finite-State Automata and Languages 359

7.6 Summary 380

7.7 Problems 381

Chapter 8 Decision Diagrams, Equivalence Checking, and Symbolic Simulation 387

8.1 Binary Decision Diagrams 388

8.2 Decision Diagram Variants 412

8.3 Decision Diagram-Based Equivalence Checking 424

8.4 Boolean Satisfiability 430

8.5 Symbolic Simulation 442

8.6 Summary 457

8.7 Problems 458

Chapter 9 Model Checking and Symbolic Computation 465

9.1 Properties, Specifications, and Logic 466

9.2 Property Checking 484

9.3 Symbolic Computation and Model Checking 494

9.4 Symbolic CTL Model Checking 513

9.5 Computational Improvements 524

9.6 Using Model-Checking Tools 529

9.7 Summary 531

9.8 Problems 531

Bibliography 539
Index 561