Timing Analysis and Simulation for Signal Integrity Engineers (美國原版)

Description

Every day, companies call upon their signal integrity engineers to make difficult decisions about design constraints and timing margins. Can I move these wires closer together? How many holes can I drill in this net? How far apart can I place these chips? Each design is unique: there’s no single recipe that answers all the questions. Today’s designs require ever greater precision, but design guides for specific digital interfaces are by nature conservative. Now, for the first time, there’s a complete guide to timing analysis and simulation that will help you manage the tradeoffs between signal integrity, performance, and cost.

 

Writing from the perspective of a practicing SI engineer and team lead, Greg Edlund of IBM presents deep knowledge and quantitative techniques for making better decisions about digital interface design. Edlund shares his insights into how and why digital interfaces fail, revealing how fundamental sources of pathological effects can combine to create fault conditions. You won’t just learn Edlund’s expert techniques for avoiding failures: you’ll learn how to develop the right approach for your own projects and environment.

 

Coverage includes

•  Systematically ensure that interfaces will operate with positive timing margin over the product’s lifetime–without incurring excess cost

•  Understand essential chip-to-chip timing concepts in the context of signal integrity

•  Collect the right information upfront, so you can analyze new designs more effectively

•  Review the circuits that store information in CMOS state machines–and how they fail

•  Learn how to time common-clock, source synchronous, and high-speed serial transfers

•  Thoroughly understand how interconnect electrical characteristics affect timing: propagation delay, impedance profile, crosstalk, resonances, and frequency-dependent loss

•  Model 3D discontinuities using electromagnetic field solvers

•  Walk through four case studies: coupled differential vias, land grid array connector, DDR2 memory data transfer, and PCI Express channel

•  Appendices present a refresher on SPICE modeling and a high-level conceptual framework for electromagnetic field behavior

Objective, realistic, and practical, this is the signal integrity resource engineers have been searching for.

 

Table of Contents

Preface xiii

Acknowledgments xvi

About the Author xix

About the Cover xx

 

Chapter 1: Engineering Reliable Digital Interfaces 1

Chapter 2: Chip-to-Chip Timing 13

Chapter 3: Inside IO Circuits 39

Chapter 4: Modeling 3D Discontinuities 73

Chapter 5: Practical 3D Examples 101

Chapter 6: DDR2 Case Study 133

Chapter 7: PCI Express Case Study 175

 

Appendix A: A Short CMOS and SPICE Primer 209

Appendix B: A Stroll Through 3D Fields 219

 

Endnotes 233

Index 235

描述

每天，公司都需要依賴其信號完整性工程師做出關於設計限制和時序裕度的困難決策。我可以將這些線路靠得更近嗎？我可以在這個網路上鑽多少個孔？我可以將這些晶片放多遠？每個設計都是獨特的：沒有一個單一的配方可以回答所有問題。如今的設計需要更高的精確度，但特定數位介面的設計指南本質上是保守的。現在，首次出現了一本完整的時序分析和模擬指南，將幫助您在信號完整性、性能和成本之間取得平衡。

從實踐信號完整性工程師和團隊負責人的角度撰寫，IBM的Greg Edlund提供了深入的知識和量化技術，以便更好地做出關於數位介面設計的決策。Edlund分享了他對數位介面失敗的洞察，揭示了如何結合基本的病態效應來創造故障狀態。您不僅會學到Edlund避免故障的專業技巧，還會學到如何為自己的項目和環境開發正確的方法。

內容包括：

- 系統性地確保介面在產品壽命內具有正確的時序裕度，而不會產生過多的成本
- 在信號完整性的背景下理解關鍵的晶片對晶片時序概念
- 提前收集正確的信息，以便更有效地分析新設計
- 審查在CMOS狀態機中存儲信息的電路，以及它們的故障原因
- 學習如何對常見時鐘、源同步和高速串行傳輸進行時序控制
- 充分了解互連電氣特性對時序的影響：傳播延遲、阻抗特性、串擾、共振和頻率依賴性損耗
- 使用電磁場求解器對三維不連續性進行建模
- 通過四個案例研究：耦合差分通孔、陣列連接器、DDR2記憶體數據傳輸和PCI Express通道
- 附錄提供SPICE建模的複習和電磁場行為的高層次概念框架
- 這是工程師一直在尋找的信號完整性資源，目標明確、實際可行。

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