FireWire System Architecture: IEEE 1394a, 2/e

MindShare Inc., Don Anderson

  • 出版商: Addison-Wesley Professional
  • 出版日期: 1998-12-27
  • 定價: USD $54.99
  • 售價: $900
  • 貴賓價: 9.5$855
  • 語言: 英文
  • 頁數: 544
  • 裝訂: Paperback
  • ISBN: 0201485354
  • ISBN-13: 9780201485356

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Table Of Contents

(Most chapters begin with an Overview.)
About This Book.

The MindShare Architecture Series
Cautionary Note.
Organization of This Book.
Part One: Introduction to FireWire (IEEE 1394).
Part Two: Serial Bus Communications.
Part Three: Serial Bus Configuration.
Part Four: Serial Bus Management.
Part Five: Registers and Configuration ROM.
Part Six: Power Management.
Appendix.
Target Audience.
Prerequisite Knowledge.
Documentation Conventions.
Labels for Multi-byte Blocks.
Hexadecimal Notation.
Binary Notation.
Decimal Notation.
Bit Versus Byte Notation.
Identification of Bit Fields (logical groups of bits or signals).
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We Want Your Feedback.

I. INTRODUCTION TO FIREWIRE (IEEE 1394a).


1. Why FireWire?
Motivations Behind FireWire Development.
Inexpensive Alternate to Parallel Buses.
Plug and Play Support.
Eliminate Host Processor/Memory Bottleneck.
High Speed Bus with Scalable Performance.
Support for Isochronous Applications.
BackPlane and Cable Environments.
Bus Bridge.
1394 Applications.
IEEE 1394 Refinements.
Primary Features.

2. Overview of the IEEE 1394 Architecture.
IEEE 1394 Overview.
Specifications and Related Documents.
IEEE 1394-1995 and the IEEE 1394a Supplement.
IEEE 1394.B.
Unit Architecture Specifications.
IEEE 1394 Topology.
Multiport Nodes and Repeaters.
Configuration.
Peer-To-Peer Transfers.
Device Bay.
The ISO/IEC 13213 Specification.
Node Architecture.
Address Space.
Transfers and Transactions.
Control and Status Registers (CSRs).
Configuration ROM.
Message Broadcast.
Interrupt Broadcast.
Automatic Configuration.

II. SERIAL BUS COMMUNICATIONS.


3. Communications Model.
Transfer Types.
Asynchronous.
Isochronous.
The Protocol Layers.
Bus Management Layer.
Transaction Layer.
Link Layer.
Physical Layer.
A Sample Asynchronous Transaction.
The Request.
The Response.
An Example Isochronous Transaction.

4. Communications Services.
Anatomy of Asynchronous Transactions.
The Request Subaction.
Response Subaction.
Anatomy of Isochronous Transactions.
Setting Up Isochronous Transactions.
Maintaining Synchronization.
Isochronous Transactions.
Isochronous Transaction Initiation & Reception.

5. Cables & Connectors.
Cable and Connector Types.
6-pin Connector (1394-1995).
Make First/Break Last Power Pins.
Optional 4-pin Connector (1394a supplement).
Positive Retention.
Cable Characteristics.
6-Conductor Cables.
4-Conductor Cables.
Device Bay.

6. The Electrical Interface.
Common Mode Signaling.
Differential Signaling.
Recognition of Device Attachment and Detachment.
IEEE 1394-1995 Device Attachment/Detachment.
IEEE 1394a Device Attachment/Detachment.
Bus Idle State.
The Port Interface.
Differential Signal Specifications.
Arbitration Signaling.
Line State Signaling (1, 0, and Z).
Line State Detection.
Reset Signaling.
Line States During Configuration.
Line States During Normal Arbitration.
Starting and Ending Packet Transmission.
Dribble Bits.
Port State Control.
Speed Signaling.
High Speed Devices Slowed Due to Topology.
Devices of Like Speed Directly Connected.
Speed Signaling Circuitry.
Data/Strobe Signaling.
NRZ Encoding.
Data-Strobe Encoding.
Gap Timing.
Cable Interface Timing Constants.
Suspend/Resume.
Cable Power.
Cable Power Requirements.
Power Class.
Power Distribution.
Bus Powered Nodes.

7. Arbitration.
Arbitration Signaling.
Arbitration Services.
Asynchronous Arbitration.
Fairness Interval.
The Acknowledge Packet and Immediate Arbitration Service.
Isochronous Arbitration.
Cycle Start and Priority Arbitration.
Combined Isochronous and Asynchronous Arbitration.
Cycle Start Skew.
1394a Arbitration Enhancements.
Acknowledge Accelerated Arbitration.
Fly-by Arbitration.
Acceleration Control.
Priority Arbitration Service.
Summary of Arbitration Types.

8. Asynchronous Packets.
Asynchronous Packets.
Data Size.
Write Packets.
Asynchronous Stream Packet.
Read Packets.
Lock Operations.
Lock Request Packet.
Lock Response Packet.
Response Codes.
Acknowledge Packet.
Asynchronous Transaction Summary.
Write Transactions.
Summary of Read and Lock Transactions.
Cycle Start Packet.

9. Isochronous Packet.
Stream Data Packet.
Isochronous Data Packet Size.
Isochronous Transaction Summary.

10. PHY Packet Format.
PHY Packet Format.
Self-ID Packets.
Self-ID Packet Zero.
Self-ID Packets One, Two, and Three (1394-1995).
Self-ID Packets One and Two (1394a).
Link-on Packet.
PHY Configuration Packet.
Force Root Node.
Gap Count Optimization.
Extended PHY Packets.
Ping Packet.
Remote Access Packet.
Remote Reply Packet.
Remote Command Packet.
Remote Confirmation Packet.
Resume Packet.

11. Link to PHY Interface.
The Interface Signals.
Sharing the Interface.
PHY Initiated Transfers.
Link Initiated Transfers.
Determining Transfer Rate Between Link and PHY.
Powering the Link.
Packet Transmission.
Link Issues Request.
Receiving Packets.
PHY Reports Status.
ARB_RESET_GAP.
SUBACTION_GAP.
BUS_RESET_START.
PHY_INTERRUPT.
Accelerated Arbitration Control.
Accessing the PHY Registers.
PHY Register Reads.
PHY Register Writes.
Electrical Isolation Between PHY and Link.

12. Transaction Retry.
Busy Retry.
The First Packet Transmission Attempt.
Single Phase Retry.
Dual Phase Retry.
Transactions Errors.
Packet Transmission Errors.
Packet Error Handling Summary.

III. SERIAL BUS CONFIGURATION.


13. Configuration Process.
Bus Initialization (Bus Reset).
Tree Identification (The Family Tree).
Self Identification.
Bus Management.

14. Bus Reset (Initialization).
Sources of Bus Reset.
Power Status Change.
Bus Reset Signaled by Attached Node.
Node Attachment or Removal.
MAX_ARB_STATE_TIME Expires.
Software Initiated Bus Reset.
Bus Reset Signaling.
Effects of Bus Reset.
Topology Information Cleared.
PHY Register Changes.
CSR Register Changes.
1394-1995 and Reset Runaway.
Problem One: The Reset Storm.
The 1394a Solution: Debounce Port Status Signal.
Problem Two: Recognition of Connection Change Not Symmetric.
The Solution: Slow Node Accepts Fast Node's Reset Signaling.
Problem Three: Reset Signaled During Packet.
Transmission.

15. Tree Identification.
Tree ID Signaling.
The Tree ID Process.
Leaf Nodes Try to Find Their Parents.
Parents Identify Their Children.
Three Example Scenarios.
Scenario One.
Leaf Nodes Signal Parent_Notify.
Branch Nodes Locate Their Parents.
Scenario Two.
Leaf Nodes Locate Their Parents.
Root Contention.
Scenario Three.
Force Root Delay.
Leaf Nodes Attempt to Locate Their Parents.
Branch Nodes Attempt to Locate Their Parents.
Looped Topology Detection.

16. Self Identification.
Self-Identification Signaling.
Physical ID Selection.
Second and Subsequent Physical ID Assignment.
Self-ID Packets.
Self-ID Packet Zero.
Self-ID Packets One and Two (1394a).
Who Uses the Self-ID Packet Information.

IV. SERIAL BUS MANAGEMENT.


17. Cycle Master.
Determining and Enabling the Cycle Master.
Cycle Start Packet.

18. Isochronous Resource Manager.
Determining the Isochronous Resource Manager.
Minimum Requirements of Isochronous Resource Managers.
Enabling the Cycle Master.
Resource Allocation Registers.
Channel Allocation.
Bus Bandwidth Allocation.
Reallocation of Isochronous Resources.
Power Management.

19. Bus Manager.
Determining the Bus Manager.
Power Management.
Power Management by Bus Manager Node.
Power Management by IRM Node.
The Topology Map.
Accessing the Topology Map.
Gap Count Optimization.
The Speed Map.
Accessing the Speed Map.
Bus Bandwidth Set-Aside.

20. Bus Management Services.
Serial Bus Control Requests.
Bus Reset Control Request.
Initialize Control Request.
Link-On Control Request.
Present Status.
PHY Configuration Request.
Serial Bus Control Confirmations.
Serial Bus Event Indication.

V. REGISTERS & ROM.


21. CSR Architecture.
Core Registers.
Effect of Reset on the CSRs.
State Register (State_Clear & State_Set).
Node_IDS Register.
Reset_Start Register.
Indirect_Address and Indirect_Data Registers.
Split_Timeout Register.
Argument, Test_Start, and Test_Status Registers.
Units_Base, Units_Bound, Memory_Base, and Memory_Bound Registers.
Interrupt_Target and Interrupt_Mask Registers.
Clock_Value, Clock_Tick_Period, Clock_Strobe_Arrived, and Clock_Info Registers.
Message_Request & Message_Response Registers.
Serial Bus Dependent Registers.
Cycle_Time & Bus_Time Registers.
Power_Fail_Imminent & Power_Source Registers.
Busy_Timeout Register.
Bus_Manager_ID Register.
Bandwidth_Available Register.
Channels_Available Register.
Maint_Control Register.
Maint_Utility Register.
Unit Registers.
Topology Map.
Speed Map.

22. PHY Registers.
1394-1995 PHY Register Map.
Port Status Registers.
PHY Configuration Packet.
1394a PHY Register Map.
Page Select.

23. Configuration ROM.
Minimal ROM Format.
General ROM Format.
Header Information.
Bus_Info_Block (1394-1995).
Bus Info Block (1394a).
Root_Directory.
Company ID Value Administration.

VI. POWER MANAGEMENT.


24. Introduction to Power Management.
Review of 1394-1995 Power-Related Issues.
Goals of the 1394a Power Extensions.

25. Cable Power Distribution.
Power Distribution.
Power Class Codes.
Power Providers.
Power Consumer.
Self-Powered Nodes (Non Power Providers).
Local Power Down Summary.

26. Suspend & Resume.
Suspending a Port.
Suspending Via the Suspend Command Packet.
Suspending Via RX_SUSPEND.
The BIAS Handshake.
Suspending Via Port Disable.
Port Suspend Via Unexpected Loss of Bias.
Resuming Full Operation.
Resuming Via Resume Packet.
Resuming Via Resume Port Command Packet.
Resuming Via Port Events.

27. Power State Management.
Power Management.
Power States.
New CSRs.
New ROM Entries.

Appendix: Example 1394 Chip Solutions.
Overview.
1394 in the PC.
TSB12LV22 / OHCI-Lynx.
Features.
Overview.
TSB41LV03.
Putting it all Together.
1394 in the Digital Camera.
TSB12LV31 - GPLynx.
TSB21LV03A.
Putting it all Together.
For More Information.

Appendix: Glossary.
Index. 0201485354T04062001


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