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商品描述
This book addresses an often-neglected aspect of the creation of VHDL designs. A VHDL description is also source code, and VHDL designers can use the best practices of software development to write high-quality code and to organize it in a design. This book presents this unique set of skills, teaching VHDL designers of all experience levels how to apply the best design principles and coding practices from the software world to the world of hardware. The concepts introduced here will help readers write code that is easier to understand and more likely to be correct, with improved readability, maintainability, and overall quality.
After a brief review of VHDL, the book presents fundamental design principles for writing code, discussing such topics as design, quality, architecture, modularity, abstraction, and hierarchy. Building on these concepts, the book then introduces and provides recommendations for each basic element of VHDL code, including statements, design units, types, data objects, and subprograms. The book covers naming data objects and functions, commenting the source code, and visually presenting the code on the screen. All recommendations are supported by detailed rationales. Finally, the book explores two uses of VHDL: synthesis and testbenches. It examines the key characteristics of code intended for synthesis (distinguishing it from code meant for simulation) and then demonstrates the design and implementation of testbenches with a series of examples that verify different kinds of models, including combinational, sequential, and FSM code. Examples from the book are also available on a companion website, enabling the reader to experiment with the complete source code.
商品描述(中文翻譯)
本書探討了在創建 VHDL 設計時常被忽視的一個方面。VHDL 描述也是源代碼,VHDL 設計師可以利用軟體開發的最佳實踐來編寫高品質的代碼並將其組織在設計中。本書呈現了這一獨特的技能組合,教導各種經驗水平的 VHDL 設計師如何將來自軟體世界的最佳設計原則和編碼實踐應用於硬體世界。這裡介紹的概念將幫助讀者編寫更易於理解且更有可能正確的代碼,並提高可讀性、可維護性和整體質量。
在簡要回顧 VHDL 之後,本書介紹了編寫代碼的基本設計原則,討論了設計、質量、架構、模組化、抽象和層次等主題。在這些概念的基礎上,本書隨後介紹並提供每個 VHDL 代碼基本元素的建議,包括語句、設計單元、類型、數據對象和子程序。本書涵蓋了命名數據對象和函數、對源代碼進行註解以及在螢幕上視覺呈現代碼。所有建議都有詳細的理由支持。最後,本書探討了 VHDL 的兩種用途:綜合和測試平台。它檢視了用於綜合的代碼的關鍵特徵(將其與用於模擬的代碼區分開來),然後通過一系列示例展示測試平台的設計和實現,這些示例驗證了不同類型的模型,包括組合邏輯、時序邏輯和有限狀態機(FSM)代碼。本書中的示例也可在伴隨網站上獲得,讓讀者能夠實驗完整的源代碼。
