PCI Express System Architecture (Paperback)

Mindshare Inc., Ravi Budruk, Don Anderson, Tom Shanley

  • 出版商: Addison Wesley
  • 出版日期: 2003-09-14
  • 定價: $3,980
  • 售價: 7.8$3,120
  • 貴賓價: 7.4$2,964
  • 語言: 英文
  • 頁數: 1120
  • 裝訂: Paperback
  • ISBN: 0321156307
  • ISBN-13: 9780321156303

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Summary

"We have always recommended these books to our customers and even our own engineers for developing a better understanding of technologies and specifications. We find the latest PCI Express book from MindShare to have the same content and high quality as all the others."
—Nader Saleh, CEO/President, Catalyst Enterprises, Inc.

PCI Express is the third-generation Peripheral Component Inter-connect technology for a wide range of systems and peripheral devices. Incorporating recent advances in high-speed, point-to-point interconnects, PCI Express provides significantly higher performance, reliability, and enhanced capabilities—at a lower cost—than the previous PCI and PCI-X standards. Therefore, anyone working on next-generation PC systems, BIOS and device driver development, and peripheral device design will need to have a thorough understanding of PCI Express.

PCI Express System Architecture provides an in-depth description and comprehensive reference to the PCI Express standard. The book contains information needed for design, verification, and test, as well as background information essential for writing low-level BIOS and device drivers. In addition, it offers valuable insight into the technology's evolution and cutting-edge features.

Following an overview of the PCI Express architecture, the book moves on to cover transaction protocols, the physical/electrical layer, power management, configuration, and more. Specific topics covered include:

  • Split transaction protocol
  • Packet format and definition, including use of each field
  • ACK/NAK protocol
  • Traffic Class and Virtual Channel applications and use
  • Flow control initialization and operation
  • Error checking mechanisms and reporting options
  • Switch design issues
  • Advanced Power Management mechanisms and use
  • Active State Link power management
  • Hot Plug design and operation
  • Message transactions
  • Physical layer functions
  • Electrical signaling characteristics and issues
  • PCI Express enumeration procedures
  • Configuration register definitions

Thoughtfully organized, featuring a plethora of illustrations, and comprehensive in scope, PCI Express System Architecture is an essential resource for anyone working with this important technology.

MindShare's PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Books in the series are intended for use by hardware and software designers, programmers, and support personnel.

Table of Contents

About This Book.

The MindShare Architecture Series.

Cautionary Note.

Intended Audience.

Prerequisite Knowledge.

Topics and Organization.

Documentation Conventions.

PCI Express(TM).

Hexadecimal Notation.

Binary Notation.

Decimal Notation.

Bits Versus Bytes Notation.

Bit Fields.

Active Signal States.

Visit Our Web Site.

We Want Your Feedback.

I. THE BIG PICTURE.

1. Architectural Perspective.

Introduction To PCI Express.

The Role of the Original PCI Solution.

Don't Throw Away What is Good! Keep It.

Make Improvements for the Future.

Looking into the Future.

Predecessor Buses Compared.

Author's Disclaimer.

Bus Performances and Number of Slots Compared.

PCI Express Aggregate Throughput.

Performance Per Pin Compared 14I/O Bus Architecture Perspective.

33 MHz PCI Bus Based System.

Electrical Load Limit of a 33 MHz PCI Bus.

PCI Transaction Model — Programmed IO.

PCI Transaction Model — Peer-to-Peer.

PCI Bus Arbitration.

PCI Delayed Transaction Protocol.

PCI Retry Protocol.

PCI Disconnect Protocol.

PCI Interrupt Handling.

PCI Error Handling.

PCI Address Space Map.

PCI Configuration Cycle Generation.

PCI Function Configuration Register Space.

PCI Programming Model.

Limitations of a 33 MHz PCI System.

Latest Generation of Intel PCI Chipsets.

66 MHz PCI Bus Based System.

Limitations of 66 MHz PCI bus.

Limitations of PCI Architecture.

66 MHz and 133 MHz PCI-X 10 Bus Based Platforms.

PCI-X Features.

PCI-X Requester/Completer Split Transaction Model.

DDR and QDR PCI-X 20 Bus Based Platforms.

The PCI Express Way.

The Link — A Point-to-Point Interconnect.

Differential Signaling.

Switches Used to Interconnect Multiple Devices.

Packet Based Protocol.

Bandwidth and Clocking.

Address Space.

PCI Express Transactions.

PCI Express Transaction Model.

Error Handling and Robustness of Data Transfer.

Quality of Service (QoS), Traffic Classes (TCs) and Virtual Channels (VCs).

Flow Control.

MSI Style Interrupt Handling Similar to PCI-X.

Power Management.

Hot Plug Support.

PCI Compatible Software Model.

Mechanical Form Factors.

PCI-like Peripheral Card and Connector.

Mini PCI Express Form Factor.

Mechanical Form Factors Pending Release.

NEWCARD Form Factor.

Server IO Module (SIOM) Form Factor.

PCI Express Topology.

Enumerating the System.

PCI Express System Block Diagram.

Low Cost PCI Express Chipset.

High-End Server System.

PCI Express Specifications.

2. Architecture Overview.

Introduction to PCI Express Transactions.

PCI Express Transaction Protocol.

Non-Posted Read Transactions.

Non-Posted Read Transaction for Locked Requests.

Non-Posted Write Transactions.

Posted Memory Write Transactions.

Posted Message Transactions.

Some Examples of Transactions.

Memory Read Originated by CPU, Targeting an Endpoint.

Memory Read Originated by Endpoint, Targeting System Memory.

IO Write Initiated by CPU, Targeting an Endpoint.

Memory Write Transaction Originated by CPU and Targeting an Endpoint.

PCI Express Device Layers.

Overview.

Transmit Portion of Device Layers.

Receive Portion of Device Layers.

Device Layers and their Associated Packets.

Transaction Layer Packets (TLPs).

TLP Packet Assembly.

TLP Packet Disassembly.

Data Link Layer Packets (DLLPs).

DLLP Assembly.

DLLP Disassembly.

Physical Layer Packets (PLPs).

Function of Each PCI Express Device Layer.

Device Core / Software Layer.

Transmit Side.

Receive Side.

Transaction Layer.

Transmit Side.

Receiver Side.

Flow Control.

Quality of Service (QoS).

Traffic Classes (TCs) and Virtual Channels (VCs).

Port Arbitration and VC Arbitration.

Transaction Ordering.

Power Management.

Configuration Registers.

Data Link Layer.

Transmit Side.

Receive Side.

Data Link Layer Contribution to TLPs and DLLPs.

Non-Posted Transaction Showing ACK-NAK Protocol.

Posted Transaction Showing ACK-NAK Protocol.

Other Functions of the Data Link Layer.

Physical Layer.

Transmit Side.

Receive Side.

Link Training and Initialization.

Link Power Management.

Reset.

Electrical Physical Layer.

Example of a Non-Posted Memory Read Transaction.

Memory Read Request Phase.

Completion with Data Phase.

Hot Plug.

PCI Express Performance and Data Transfer Efficiency.

II. TRANSACTION PROTOCOL.

3. Address Spaces <38> Transaction Routing.

Introduction.

Receivers Check For Three Types of Link Traffic.

Multi-port Devices Assume the Routing Burden.

Endpoints Have Limited Routing Responsibilities.

System Routing Strategy Is Programmed.

Two Types of Local Link Traffic.

Ordered Sets.

Data Link Layer Packets (DLLPs).

Transaction Layer Packet Routing Basics.

TLPs Used to Access Four Address Spaces.

Split Transaction Protocol Is Used.

Split Transactions: Better Performance, More Overhead.

Write Posting: Sometimes a Completion Isn't Needed.

Three Methods of TLP Routing.

PCI Express Routing Is Compatible with PCI.

PCI Express Adds Implicit Routing for Messages.

Why Were Messages Added to PCI Express Protocol?

How Implicit Routing Helps with Messages.

Header Fields Define Packet Format and Routing.

Using TLP Header Information: Overview.

General.

Header Type/Format Field Encodings.

Applying Routing Mechanisms.

Address Routing.

Memory and IO Address Maps.

Key TLP Header Fields in Address Routing.

TLPs with 3DW, 32-Bit Address.

TLPs With 4DW, 64-Bit Address.

An Endpoint Checks an Address-Routed TLP.

A Switch Receives an Address Routed TLP: Two Checks.

General.

Other Notes About Switch Address-Routing.

ID Routing.

ID Bus Number, Device Number, Function Number Limits.

Key TLP Header Fields in ID Routing.

3DW TLP, ID Routing.

4DW TLP, ID Routing.

An Endpoint Checks an ID-Routed TLP.

A Switch Receives an ID-Routed TLP: Two Checks.

Other Notes About Switch ID Routing.

Implicit Routing.

Only Messages May Use Implicit Routing.

Messages May Also Use Address or ID Routing.

Routing Sub-Field in Header Indicates Routing Method.

Key TLP Header Fields in Implicit Routing.

Message Type Field Summary.

An Endpoint Checks a TLP Routed Implicitly.

A Switch Receives a TLP Routed Implicitly.

Plug-And-Play Configuration of Routing Options.

Routing Configuration Is PCI-Compatible.

Two Configuration Space Header Formats: Type 0, Type 1.

Routing Registers Are Located in Configuration Header.

Base Address Registers (BARs): Type 0, 1 Headers.

General.

BAR Setup Example One: 1MB, Prefetchable Memory Request.

BAR Setup Example Two: 64-Bit, 64MB Memory Request.

BAR Setup Example Three: 256-Byte IO Request.

Base/Limit Registers, Type 1 Header Only.

General.

Prefetchable Memory Base/Limit Registers.

Non-Prefetchable Memory Base/Limit Registers.

IO Base/Limit Registers.

Bus Number Registers, Type 1 Header Only.

Primary Bus Number.

Secondary Bus Number.

Subordinate Bus Number.

A Switch Is a Two-Level Bridge Structure.

4. Packet-Based Transactions.

Introduction to the Packet-Based Protocol.

Why Use A Packet-Based Transaction Protocol.

Packet Formats Are Well Defined.

Framing Symbols Indicate Packet Boundaries.

CRC Protects Entire Packet.

Transaction Layer Packets.

TLPs Are Assembled And Disassembled.

Device Core Requests Access to Four Spaces.

TLP Transaction Variants Defined.

TLP Structure.

Generic TLP Header Format.

Generic Header Field Summary.

Header Type/Format Field Encodings.

The Digest and ECRC Field.

ECRC Generation and Checking.

Who Can Check ECRC?

Using Byte Enables.

Byte Enable Rules.

Transaction Descriptor Fields.

Transaction ID.

Traffic Class.

Transaction Attributes.

Additional Rules For TLPs With Data Payloads.

Building Transactions: TLP Requests <38> Completions.

IO Requests.

IO Request Header Format.

Definitions Of IO Request Header Fields.

Memory Requests.

Description of 3DW And 4DW Memory Request Header Fields.

Memory Request Notes.

Configuration Requests.

Definitions Of Configuration Request Header Fields.

Configuration Request Notes.

Completions.

Definitions Of Completion Header Fields.

Summary of Completion Status Codes.

Calculating The Lower Address Field (Byte 11, bits 7:0).

Using The Byte Count Modified Bit.

Data Returned For Read Requests.

Receiver Completion Handling Rules.

Message Requests.

Definitions Of Message Request Header Fields.

Message Notes.

INTx Interrupt Signaling.

Power Management Messages.

Error Messages.

Unlock Message.

Slot Power Limit Message.

Hot Plug Signaling Message.

Data Link Layer Packets.

Types Of DLLPs.

DLLPs Are Local Traffic.

Receiver handling of DLLPs.

Sending A Data Link Layer Packet.

Fixed DLLP Packet Size: 8 Bytes.

DLLP Packet Types.

Ack Or Nak DLLP Packet Format.

Definitions Of Ack Or Nak DLLP Fields.

Power Management DLLP Packet Format.

Definitions Of Power Management DLLP Fields.

Flow Control Packet Format.

Definitions Of Flow Control DLLP Fields.

Vendor Specific DLLP Format.

Definitions Of Vendor Specific DLLP Fields.

5. ACK/NAK Protocol.

Reliable Transport of TLPs Across Each Link.

Elements of the ACK/NAK Protocol.

Transmitter Elements of the ACK/NAK Protocol.

Replay Buffer.

NEXT_TRANSMIT_SEQ Counter.

LCRC Generator.

REPLAY_NUM Count.

REPLAY_TIMER Count.

ACKD_SEQ Count.

DLLP CRC Check.

Receiver Elements of the ACK/NAK Protocol.

Receive Buffer.

LCRC Error Check.

NEXT_RCV_SEQ Count.

Sequence Number Check.

NAK_SCHEDULED Flag.

ACKNAK_LATENCY_TIMER.

ACK/NAK DLLP Generator.

ACK/NAK DLLP Format.

ACK/NAK Protocol Details.

Transmitter Protocol Details.

Sequence Number.

32-Bit LCRC.

Replay (Retry) Buffer.

General.

Replay Buffer Sizing.

Transmitter's Response to an ACK DLLP.

General.

Purging the Replay Buffer.

Examples of Transmitter ACK DLLP Processing.

Example 1.

Example 2.

Transmitter's Response to a NAK DLLP.

TLP Replay.

Efficient TLP Replay.

Example of Transmitter NAK DLLP Processing.

Repeated Replay of TLPs.

What Happens After the Replay Number Rollover?

Transmitter's Replay Timer.

REPLAY_TIMER Equation.

REPLAY_TIMER Summary Table.

Transmitter DLLP Handling.

Receiver Protocol Details.

TLP Received at Physical Layer.

Received TLP Error Check.

Next Received TLP's Sequence Number.

Receiver Schedules An ACK DLLP.

Example of Receiver ACK Scheduling.

NAK Scheduled Flag.

Receiver Schedules a NAK.

Receiver Sequence Number Check.

Receiver Preserves TLP Ordering.

Example of Receiver NAK Scheduling.

Receivers ACKNAK_LATENCY_TIMER.

ACKNAK_LATENCY_TIMER Equation.

ACKNAK_LATENCY_TIMER Summary Table.

Error Situations Reliably Handled by ACK/NAK Protocol.

ACK/NAK Protocol Summary.

Transmitter Side.

Non-Error Case (ACK DLLP Management).

Error Case (NAK DLLP Management).

Receiver Side.

Non-Error Case.

Error Case.

Recommended Priority To Schedule Packets.

Some More Examples.

Lost TLP.

Lost ACK DLLP or ACK DLLP with CRC Error.

Lost ACK DLLP followed by NAK DLLP.

Switch Cut-Through Mode.

Without Cut-Through Mode.

Background.

Possible Solution.

Switch Cut-Through Mode.

Background.

Example That Demonstrates Switch Cut-Through Feature.

6. QoS/TCs/VCs and Arbitration

Quality of Service.

Isochronous Transaction Support.

Synchronous Versus Isochronous Transactions.

Isochronous Transaction Management.

Differentiated Services.

Perspective on QOS/TC/VC and Arbitration.

Traffic Classes and Virtual Channels.

VC Assignment and TC Mapping.

Determining the Number of VCs to be Used.

Assigning VC Numbers (IDs).

Assigning TCs to each VC — TC/VC Mapping.

Arbitration.

Virtual Channel Arbitration.

Strict Priority VC Arbitration.

Low- and High-Priority VC Arbitration.

Hardware Fixed Arbitration Scheme.

Weighted Round Robin Arbitration Scheme.

Round Robin Arbitration (Equal or Weighted) for All VCs.

Loading the Virtual Channel Arbitration Table.

VC Arbitration within Multiple Function Endpoints.

Port Arbitration.

The Port Arbitration Mechanisms.

Non-Configurable Hardware-Fixed Arbitration.

Weighted Round Robin Arbitration.

Time-Based, Weighted Round Robin Arbitration.

Loading the Port Arbitration Tables.

Switch Arbitration Example.

7. Flow Control.

Flow Control Concept.

Flow Control Buffers.

VC Flow Control Buffer Organization.

Flow Control Credits.

Maximum Flow Control Buffer Size.

Introduction to the Flow Control Mechanism.

The Flow Control Elements.

Transmitter Elements.

Receiver Elements.

Flow Control Packets.

Operation of the Flow Control Model — An Example.

Stage 1 — Flow Control Following Initialization.

Stage 2 — Flow Control Buffer Fills Up.

Stage 3 — The Credit Limit count Rolls Over.

Stage 4 — FC Buffer Overflow Error Check.

Infinite Flow Control Advertisement.

Who Advertises Infinite Flow Control Credits?

Special Use for Infinite Credit Advertisements.

Header and Data Advertisements May Conflict.

The Minimum Flow Control Advertisement.

Flow Control Initialization.

The FC Initialization Sequence.

FC Init1 Packets Advertise Flow Control Credits Available.

FC Init2 Packets Confirm Successful FC Initialization.

Rate of FC_INIT1 and FC_INIT2 Transmission.

Violations of the Flow Control Initialization Protocol.

Flow Control Updates Following FC_INIT.

FC_Update DLLP Format and Content.

Flow Control Update Frequency.

Immediate Notification of Credits Allocated.

Maximum Latency Between Update Flow Control DLLPs.

Calculating Update Frequency Based on Payload Size and Link Width.

Error Detection Timer — A Pseudo Requirement.

8. Transaction Ordering.

Introduction.

Producer/Consumer Model.

Native PCI Express Ordering Rules.

Producer/Consumer Model with Native Devices.

Relaxed Ordering.

RO Effects on Memory Writes and Messages.

RO Effects on Memory Read Transactions.

Summary of Strong Ordering Rules.

Modified Ordering Rules Improve Performance.

Strong Ordering Can Result in Transaction Blocking.

The Problem.

The Weakly Ordered Solution.

Order Management Accomplished with VC Buffers.

Summary of Modified Ordering Rules.

Support for PCI Buses and Deadlock Avoidance.

9. Interrupts.

Two Methods of Interrupt Delivery.

Message Signaled Interrupts.

The MSI Capability Register Set.

Capability ID.

Pointer To Next New Capability.

Message Control Register.

Message Address Register.

Message Data Register.

Basics of MSI Configuration.

Basics of Generating an MSI Interrupt Request.

Memory Write Transaction (MSI).

Multiple Messages.

Memory Synchronization When Interrupt Handler Entered.

The Problem.

Solving the Problem.

Interrupt Latency.

MSI Results In ECRC Error.

Some Rules, Recommendations, etc.

Legacy PCI Interrupt Delivery.

Background — PCI Interrupt Signaling.

Device INTx# Pins.

Determining if a Function Uses INTx# Pins.

Interrupt Routing.

Associating the INTx# Line to an IRQ Number.

INTx# Signaling.

Interrupt Disable.

Interrupt Status.

Virtual INTx Signaling.

Virtual INTx Wire Delivery.

Collapsing INTx Signals within a Bridge.

INTx Message Format.

Devices May Support Both MSI and Legacy Interrupts.

Special Consideration for Base System Peripherals.

Example System.

10. Error Detection and Handling.

Background.

Introduction to PCI Express Error Management.

PCI Express Error Checking Mechanisms.

Transaction Layer Errors.

Data Link Layer Errors.

Physical Layer Errors.

Error Reporting Mechanisms.

Error Handling Mechanisms.

Sources of PCI Express Errors.

ECRC Generation and Checking.

Data Poisoning (Optional).

TC to VC Mapping Errors.

Link Flow Control-Related Errors.

Malformed Transaction Layer Packet (TLP).

Split Transaction Errors.

Unsupported Request.

Completer Abort.

Unexpected Completion.

Completion Time-out.

Error Classifications.

Correctable Errors.

Uncorrectable Non-Fatal Errors.

Uncorrectable Fatal Errors.

How Errors are Reported.

Error Messages.

Completion Status.

Baseline Error Detection and Handling.

PCI-Compatible Error Reporting Mechanisms.

Configuration Command and Status Registers.

PCI Express Baseline Error Handling.

Enabling/Disabling Error Reporting.

Enabling Error Reporting — Device Control Register.

Error Status — Device Status Register.

Link Errors.

Root's Response to Error Message.

Advanced Error Reporting Mechanisms.

ECRC Generation and Checking.

Handling Sticky Bits.

Advanced Correctable Error Handling.

Advanced Correctable Error Status.

Advanced Correctable Error Reporting.

Advanced Uncorrectable Error Handling.

Advanced Uncorrectable Error Status.

Selecting the Severity of Each Uncorrectable Error.

Uncorrectable Error Reporting.

Error Logging.

Root Complex Error Tracking and Reporting.

Root Complex Error Status Registers.

Advanced Source ID Register.

Root Error Command Register.

Reporting Errors to the Host System.

Summary of Error Logging and Reporting.

III. THE PHYSICAL LAYER.

11. Physical Layer Logic.

Physical Layer Overview.

Disclaimer.

Transmit Logic Overview.

Receive Logic Overview.

Physical Layer Link Active State Power Management.

Link Training and Initialization.

Transmit Logic Details.

Tx Buffer.

Multiplexer (Mux) and Mux Control Logic.

General.

Definition of Characters and Symbols.

Byte Striping (Optional).

Packet Format Rules.

General Packet Format Rules.

x1 Packet Format Example.

x4 Packet Format Rules.

x4 Packet Format Example.

x8, x12, x16 or x32 Packet Format Rules.

x8 Packet Format Example.

Scrambler.

Purpose of Scrambling Outbound Transmission.

Scrambler Algorithm.

Some Scrambler implementation rules.

Disabling Scrambling.

8b/10b Encoding.

General.

Purpose of Encoding a Character Stream.

Properties of 10-bit (10b) Symbols.

Preparing 8-bit Character Notation.

Disparity.

Definition.

Two Categories of 8-bit Characters.

CRD (Current Running Disparity).

8b/10b Encoding Procedure.

Example Encodings.

Example Transmission.

The Lookup Tables.

Control Character Encoding.

Ordered-Sets.

General.

TS1 and TS2 Ordered-Sets.

SKIP Ordered-Set.

Electrical Idle Ordered-Set.

FTS Ordered-Set.

Parallel-to-Serial Converter (Serializer).

Differential Transmit Driver.

Transmit (Tx) Clock.

Other Miscellaneous Transmit Logic Topics.

Logical Idle Sequence.

Inserting Clock Compensation Zones.

Background.

SKIP Ordered-Set Insertion Rules.

Receive Logic Details.

Differential Receiver.

Rx Clock Recovery.

General.

Achieving Bit Lock.

Losing Bit Lock.

Regaining Bit Lock.

Serial-to-Parallel converter (Deserializer).

Symbol Boundary Sensing (Symbol Lock).

Receiver Clock Compensation Logic.

Background.

The Elastic Buffer's Role in the Receiver.

Lane-to-Lane De-Skew.

Not a Problem on a Single-Lane Link.

Flight Time Varies from Lane-to-Lane.

If Lane Data Is Not Aligned, Byte Unstriping Wouldn't Work.

TS1/TS2 or FTS Ordered-Sets Used to De-Skew Link.

De-Skew During Link Training, Retraining and L0s Exit.

Lane-to-Lane De-Skew Capability of Receiver.

8b/10b Decoder.

General.

Disparity Calculator.

Code Violation and Disparity Error Detection.

General.

Code Violations.

Disparity Errors.

De-Scrambler.

Some De-Scrambler Implementation Rules.

Disabling De-Scrambling.

Byte Un-Striping.

Filter and Packet Alignment Check.

Receive Buffer (Rx Buffer).

Physical Layer Error Handling.

Response of Data Link Layer to 'Receiver Error' Indication.

12. Electrical Physical Layer.

Electrical Physical Layer Overview.

High Speed Electrical Signaling.

Clock Requirements.

General.

Spread Spectrum Clocking (SSC).

Impedance and Termination.

Transmitter Impedance Requirements.

Receiver Impedance Requirements.

DC Common Mode Voltages.

Transmitter DC Common Mode Voltage.

Receiver DC Common Mode Voltage.

ESD and Short Circuit Requirements.

Receiver Detection.

General.

With a Receiver Attached.

Without a Receiver Attached.

Procedure To Detect Presence or Absence of Receiver.

Differential Drivers and Receivers.

Advantages of Differential Signaling.

Differential Voltages.

Differential Voltage Notation.

General.

Differential Peak Voltage.

Differential Peak-to-Peak Voltage.

Common Mode Voltage.

Electrical Idle.

Transmitter Responsibility.

Receiver Responsibility.

Power Consumed When Link Is in Electrical Idle State.

Electrical Idle Exit.

Transmission Line Loss on Link.

AC Coupling.

De-Emphasis (or Pre-Emphasis).

What is De-Emphasis?

What is the Problem Addressed By De-emphasis?

Solution.

Beacon Signaling.

General.

Properties of the Beacon Signal.

LVDS Eye Diagram.

Jitter, Noise, and Signal Attenuation.

The Eye Test.

Optimal Eye.

Jitter Widens or Narrows the Eye Sideways.

Noise and Signal Attenuation Heighten the Eye.

Transmitter Driver Characteristics.

General.

Transmit Driver Compliance Test and Measurement Load.

Input Receiver Characteristics.

Electrical Physical Layer State in Power States.

13. System Reset

Two Categories of System Reset.

Fundamental Reset.

Methods of Signaling Fundamental Reset.

PERST# Type Fundamental Reset Generation.

Autonomous Method of Fundamental Reset Generation.

In-Band Reset or Hot Reset.

Response to Receiving a Hot Reset Command.

Switches Generate Hot Reset on Their Downstream Ports.

Bridges Forward Hot Reset to the Secondary Bus.

How Does Software Tell a Device (eg Switch or Root Complex) to Generate Hot Reset?

Reset Exit.

Link Wakeup from L2 Low Power State.

Device Signals Wakeup.

Power Management Software Generates Wakeup Event.

14. Link Initialization <38> Training.

Link Initialization and Training Overview.

General.

Ordered-Sets Used During Link Training and Initialization.

TS1 and TS2 Ordered-Sets.

Electrical Idle Ordered-Set.

FTS Ordered-Set.

SKIP Ordered-Set.

Link Training and Status State Machine (LTSSM).

General.

Overview of LTSSM States.

Detailed Description of LTSSM States.

Detect State.

DetectQuiet SubState.

DetectActive SubState.

Polling State.

Introduction.

PollingActive SubState.

PollingConfiguration SubState.

PollingCompliance SubState.

PollingSpeed SubState.

Configuration State.

General.