Designing Network On-Chip Architectures in the Nanoscale Era

Going beyond isolated research ideas and design experiences, Designing Network On-Chip Architectures in the Nanoscale Era covers the foundations and design methods of network on-chip (NoC) technology. The contributors draw on their own lessons learned to provide strong practical guidance on various design issues.

Exploring the design process of the network, the first part of the book focuses on basic aspects of switch architecture and design, topology selection, and routing implementation. In the second part, contributors discuss their experiences in the industry, offering a roadmap to recent products. They describe Tilera's TILE family of multicore processors, novel Intel products and research prototypes, and the TRIPS operand network (OPN). The last part reveals state-of-the-art solutions to hardware-related issues and explains how to efficiently implement the programming model at the network interface. In the appendix, the microarchitectural details of two switch architectures targeting multiprocessor system-on-chips (MPSoCs) and chip multiprocessors (CMPs) can be used as an experimental platform for running tests.

A stepping stone to the evolution of future chip architectures, this volume provides a how-to guide for designers of current NoCs as well as designers involved with 2015 computing platforms. It cohesively brings together fundamental design issues, alternative design paradigms and techniques, and the main design tradeoffs--consistently focusing on topics most pertinent to real-world NoC designers.

《在納米時代設計網絡片上系統架構》超越孤立的研究思想和設計經驗，涵蓋了網絡片上系統（NoC）技術的基礎和設計方法。作者們根據自己的經驗提供了有關各種設計問題的實用指南。

第一部分探索了網絡的設計過程，重點介紹了交換機架構和設計的基本概念、拓撲選擇和路由實現。第二部分，作者們討論了他們在行業中的經驗，提供了最新產品的路線圖。他們描述了Tilera的TILE多核處理器系列、Intel的新型產品和研究原型以及TRIPS操作數據網絡（OPN）。最後一部分介紹了與硬件相關的最新解決方案，並解釋了如何在網絡接口上高效實現編程模型。附錄中，兩種針對多處理器系統芯片（MPSoCs）和芯片多處理器（CMPs）的交換機架構的微架構細節可以作為運行測試的實驗平台。

作為未來芯片架構演進的一個里程碑，《在納米時代設計網絡片上系統架構》為當前NoC的設計師和2015年計算平台的設計師提供了一個實用指南。它統一地集合了基本設計問題、替代設計範例和技術，以及主要的設計折衷方案，始終關注對現實世界NoC設計師最相關的主題。

José Flich is an associate professor of computer architecture and technology at the Technical University of Valencia. Dr. Flich is the coordinator of the EU-funded NaNoC project; co-chair of the CAC, CASS, and INA-OCMC workshops; and co-developer of RECN, the only truly scalable congestion management technique proposed to date. He is also associate editor of the IEEE Transactions on Parallel and Distributed Systems. His research interests include high-performance interconnection networks for multiprocessor systems, clusters of workstations, and networks on-chip.

Davide Bertozzi is an assistant professor and leader of the Multi-Processor Systems-On-Chip research group at the University of Ferrara. Dr. Bertozzi is the general chair of the INA-OCMC workshop and an editorial board member of IET Computers & Digital Techniques. His research interests encompass multi-core digital integrated systems, with an emphasis on all aspects of system interconnect design.

José Flich 是西班牙瓦倫西亞理工大學的計算機架構和技術副教授。Flich 博士是歐盟資助的 NaNoC 專案的協調人；CAC、CASS 和 INA-OCMC 研討會的聯合主席；以及 RECN 的共同開發者，這是迄今為止唯一真正可擴展的擁塞管理技術。他還是《IEEE Transactions on Parallel and Distributed Systems》的副編輯。他的研究興趣包括用於多處理器系統、工作站集群和芯片內網絡的高性能互連網絡。

Davide Bertozzi 是意大利費拉拉大學的助理教授，也是多處理器系統芯片研究小組的負責人。Bertozzi 博士是 INA-OCMC 研討會的主席，並且是《IET Computers & Digital Techniques》的編輯委員會成員。他的研究興趣包括多核數字集成系統，尤其是系統互連設計的各個方面。