Verification Methodology Manual for SystemVerilog (Hardcover) (書側有霉斑,不介意在下單) (SystemVerilog 驗證方法手冊)
Janick Bergeron , Eduard Cerny , Alan Hunter , Andy Nightingale
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商品描述
Description
Functional verification remains one of the single biggest challenges in the development of complex system-on-chip (SoC) devices. Despite the introduction of successive new technologies, the gap between design capability and verification confidence continues to widen. The biggest problem is that these diverse new technologies have led to a proliferation of verification point tools, most with their own languages and methodologies.
Fortunately, a solution is at hand. SystemVerilog is a unified language that serves both design and verification engineers by including RTL design constructs, assertions and a rich set of verification constructs. SystemVerilog is an industry standard that is well supported by a wide range of verification tools and platforms. A single language fosters the development of a unified simulation-based verification tool or platform.
Consolidation of point tools into a unified platform and convergence to a unified language enable the development of a unified verification methodology that can be used on a wide range of SoC projects. ARM and Synopsys have worked together to define just such a methodology in the Verification Methodology Manual for SystemVerilog. This book is based upon best verification practices by ARM, Synopsys and their customers.
Verification Methodology Manual for SystemVerilog is a blueprint for verification success, guiding SoC teams in building a reusable verification environment taking full advantage of design-for-verification techniques, constrained-random stimulus generation, coverage-driven verification, formal verification and other advanced technologies to help solve their current and future verification problems.
This book is appropriate for anyone involved in the design or verification of a complex chip or anyone who would like to know more about the capabilities of SystemVerilog. Following the Verification Methodology Manual for SystemVerilog will give SoC development teams and project managers the confidence needed to tape out a complex design, secure in the knowledge that the chip will function correctly in the real world.
Written for:Design automation verification engineersKeywords:
Assertion-based verification Description language Functional verification Test benches Verification standards system-on-chip
Table of contents
Introduction. -Verification Planning. -Assertions. -Testbench Infrastructure. -Stimulus and Response. -Coverage-Driven Verification. -Assertions for Formal Tools. -System-Level Verification. -Processor Integration Verification. -Appendix A: VMM Standard Library Specification. -Appendix B: VMM Checker Library. -Appendix C: XVC Standard Library Specification. -Appendix D: Software Test Framework.
商品描述(中文翻譯)
描述
功能驗證仍然是開發複雜系統單晶片(SoC)設備中最大的挑戰之一。儘管引入了連續的新技術,但設計能力和驗證信心之間的差距仍在擴大。最大的問題是這些多樣化的新技術導致了驗證點工具的激增,大多數具有自己的語言和方法論。
幸運的是,有一個解決方案。SystemVerilog是一種統一的語言,通過包含RTL設計結構、斷言和豐富的驗證結構,為設計和驗證工程師提供服務。SystemVerilog是一個行業標準,得到了廣泛的驗證工具和平台的支持。一種語言促進了統一的基於仿真的驗證工具或平台的開發。
點工具的整合到一個統一的平台和收斂到一個統一的語言,使得可以在各種SoC項目上使用統一的驗證方法論的開發成為可能。ARM和Synopsys合作制定了《SystemVerilog驗證方法論手冊》中的這種方法論。本書基於ARM、Synopsys及其客戶的最佳驗證實踐。
《SystemVerilog驗證方法論手冊》是驗證成功的藍圖,指導SoC團隊構建可重用的驗證環境,充分利用設計驗證技術、受限隨機刺激生成、覆蓋驅動驗證、形式驗證和其他先進技術,幫助解決他們目前和未來的驗證問題。
本書適用於任何參與複雜芯片設計或驗證的人,或者任何想了解SystemVerilog能力的人。遵循《SystemVerilog驗證方法論手冊》將使SoC開發團隊和項目經理在知道芯片在現實世界中能正確運行的情況下,有信心完成複雜設計的製作。
撰寫對象:
設計自動化驗證工程師
關鍵詞:
基於斷言的驗證
描述語言
功能驗證
測試環境
驗證標準
系統單晶片