Verification Methodology Manual for SystemVerilog (Hardcover) (書側有霉斑,不介意在下單)

Janick Bergeron , Eduard Cerny , Alan Hunter , Andy Nightingale

  • 出版商: Springer
  • 出版日期: 2005-09-28
  • 售價: $1,380
  • 貴賓價: 9.8$1,352
  • 語言: 英文
  • 頁數: 510
  • 裝訂: Hardcover
  • ISBN: 0387255389
  • ISBN-13: 9780387255385
  • 相關分類: Verilog
  • 立即出貨(限量) (庫存=1)




Functional verification remains one of the single biggest challenges in the development of complex system-on-chip (SoC) devices. Despite the introduction of successive new technologies, the gap between design capability and verification confidence continues to widen. The biggest problem is that these diverse new technologies have led to a proliferation of verification point tools, most with their own languages and methodologies.

Fortunately, a solution is at hand. SystemVerilog is a unified language that serves both design and verification engineers by including RTL design constructs, assertions and a rich set of verification constructs. SystemVerilog is an industry standard that is well supported by a wide range of verification tools and platforms. A single language fosters the development of a unified simulation-based verification tool or platform.

Consolidation of point tools into a unified platform and convergence to a unified language enable the development of a unified verification methodology that can be used on a wide range of SoC projects. ARM and Synopsys have worked together to define just such a methodology in the Verification Methodology Manual for SystemVerilog. This book is based upon best verification practices by ARM, Synopsys and their customers.

Verification Methodology Manual for SystemVerilog is a blueprint for verification success, guiding SoC teams in building a reusable verification environment taking full advantage of design-for-verification techniques, constrained-random stimulus generation, coverage-driven verification, formal verification and other advanced technologies to help solve their current and future verification problems.

This book is appropriate for anyone involved in the design or verification of a complex chip or anyone who would like to know more about the capabilities of SystemVerilog. Following the Verification Methodology Manual for SystemVerilog will give SoC development teams and project managers the confidence needed to tape out a complex design, secure in the knowledge that the chip will function correctly in the real world.

Written for:
Design automation verification engineers
  • Assertion-based verification
  • Description language
  • Functional verification
  • Test benches
  • Verification standards
  • system-on-chip

Table of contents

Introduction. -Verification Planning. -Assertions. -Testbench Infrastructure. -Stimulus and Response. -Coverage-Driven Verification. -Assertions for Formal Tools. -System-Level Verification. -Processor Integration Verification. -Appendix A: VMM Standard Library Specification. -Appendix B: VMM Checker Library. -Appendix C: XVC Standard Library Specification. -Appendix D: Software Test Framework.