Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications

Takayasu Sakurai, Akira Matsuzawa, Takakuni Douseki

  • 出版商: Springer
  • 出版日期: 2006-04-01
  • 售價: $1,500
  • 貴賓價: 9.8$1,470
  • 語言: 英文
  • 頁數: 411
  • 裝訂: Hardcover
  • ISBN: 0387292179
  • ISBN-13: 9780387292175
  • 相關分類: CMOS
  • 下單後立即進貨 (約5~7天)




The most important issue confronting CMOS technology is the power explosion of chips arising from the scaling law. Fully-depleted (FD) SOI technology provides a promising low-power solution to chip implementation. Ultralow-power VLSIs, which have a power consumption of less than 10 mW, will be key components of terminals in the coming ubiquitous-IT society. Fully-depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications addresses the problem of reducing the supply voltage of conventional circuits for ultralow-power operation and explains power-efficient MTCMOS circuit design for FD-SOI devices at a supply voltage of 0.5 V. The topics include the minimum required knowledge of the fabrication of SOI substrates; FD-SOI devices and the latest developments in device and process technologies; and ultralow-voltage circuits, such as digital circuits, analog/RF circuits, and DC-DC converters. Each ultra-low-power technique related to devices and circuits is fully explained using figures to help understanding. The authors present three examples of ultralow-power systems based on FD-SOI technology, providing every reader with practical knowledge on the technology and the circuits.


Table of contents

List of Contributors. Preface.

1. Introduction. 1.1 Why SOI? 1.2 What is SOI? —Structure —. 1.3 Advantages of SOI. 1.4 History of the Development of SOI Technology. 1.5 Partially-Depleted (PD) and Fully-Depleted (FD) SOI . MOSFETs, and Future MOSFETs. 1.6 Summary. References.

2. FD-SOI Device and Process Technologies.
2.1 Introduction. 2.2 FD-SOI Devices. 2.3 Theoretical Basis of FD-SOI Device Operation: DC Operation. 2.4 FD-SOI CMOS Process Technology. 2.5 Summary. References

3. Ultralow-Power Circuit Design with FD-SOI Devices.
3.1 Introduction. 3.2 Ultralow-Power Short-Range Wireless Systems. 3.3 Key Design Factor for Ultralow-Power LSIs. 3.4 Ultralow-Voltage Digital-Circuit Design. 3.5 Robustness of Ultralow-Voltage Operation. 3.6 Prospects and Issues in Low-Voltage Analog Circuits. 3.7 Technology Scaling, Analog Performance, and Performance Trend for Electrical Systems. 3.8 Low-Voltage Analog Circuit. 3.9 Fully-Depleted SOI Devices for Ultralow-Power Analog Circuits. 3.10 Future Direction of RF and Mixed Signal Systems. 3.11 Summary. References.

4. 0.5-V MTCMOS/SOI Digital Circuits.
4.1 Introduction. 4.2 MTCMOS/SOI Circuits. 4.3 Adder. 4.4 Multiplier. 4.5 Memory. 4.6 Frequency Divider. 4.7 CPU. 4.8 Summary. References.

5. 0.5-1V MTCMOS/SOI Analog/RF Circuits.
5.1 Introduction. 5.2 RF Building Blocks. 5.3 AD and DA Converters. 5.4 DC-DC Converter. 5.5 I/O and ESD-Protection Circuitry for Ultralow-Power LSIs. 5.6 Summary. References

6. SPICE Model for SOI MOSFETs.
6.1 Introduction. 6.2 SPICE Model for SOI MOSFETs. 6.3 Parameter Extraction. 6.4 Example of SOI MOSFET Simulation. 6.5 Summary. References.

7. Applications.
7.1 Introduction. 7.2 1-V Bluetooth RF Transceiver and Receiver. 7.3 Solar-Powered, Radio-Controlled Watch. 7.4 Batteryless Short-Range Wireless System. 7.5 Summary. References.

8. Prospects for FD-SOI Technology.
8.1 Introduction. 8.2 Evolution of Nanoscale FD-SOI Devices. 8.3 Device and Substrate Technologies for Ultrathin-Body SOI MOSFETs. 8.4 Power-Aware Electronics and Role of FD-SOI Technology. 8.5 Summary. References.