SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and Modeling (Hardcover)
暫譯: SystemVerilog 硬體設計與建模指南

Stuart Sutherland, Simon Davidmann, Peter Flake

SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and Modeling (Hardcover)

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Description

In its updated second edition, this book has been extensively revised on a chapter by chapter basis. The book accurately reflects the syntax and semantic changes to the SystemVerilog language standard, making it an essential reference for systems professionals who need the latest version information. In addition, the second edition features a new chapter explaining the SystemVerilog "packages", a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools.

Table of Contents

Introduction to SystemVerilog.- SystemVerilog Declaration Spaces.- SystemVerilog Literal Values and Built-In Data Types.- SystemVerilog User-Defined and Enumerated Types.- SystemVerilog Arrays, Structures and Unions.- SystemVerilog Procedural Blocks, Tasks, and Functions.- SystemVerilog Procedural Statements.- Modeling Finite State Machines with SystemVerilog.- SystemVerilog Design Hierarchy.- SystemVerilog Interfaces.- A Complete Design Modeled with SystemVerilog.- Behavioral and Transaction Level Modeling.- Appendix A: The SystemVerilog Formal Definition (BNF).- Appendix B: The SystemVerilog Formal Definition (BNF).- Appendix C: A History of Superlog, The Beginning of SystemVerilog.

商品描述(中文翻譯)

**描述**

在其更新的第二版中，本書已逐章進行了廣泛的修訂。該書準確反映了 SystemVerilog 語言標準的語法和語義變更，使其成為系統專業人員獲取最新版本資訊的必備參考資料。此外，第二版新增了一章解釋 SystemVerilog 的「packages」，並新增了一個附錄，總結了全書中提出的綜合指導方針，所有的程式碼範例也已更新至最終語法，並使用最新版本的 Synopsys、Mentor 和 Cadence 工具重新執行。

**目錄**

- SystemVerilog 簡介
- SystemVerilog 聲明空間
- SystemVerilog 字面值和內建資料類型
- SystemVerilog 使用者定義和列舉類型
- SystemVerilog 陣列、結構和聯合
- SystemVerilog 程序區塊、任務和函數
- SystemVerilog 程序語句
- 使用 SystemVerilog 建模有限狀態機
- SystemVerilog 設計層次
- SystemVerilog 介面
- 使用 SystemVerilog 建模的完整設計
- 行為和交易層級建模
- 附錄 A: SystemVerilog 正式定義 (BNF)
- 附錄 B: SystemVerilog 正式定義 (BNF)
- 附錄 C: Superlog 的歷史，SystemVerilog 的開始

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