Power Distribution Network Design for VLSI

Qing K. Zhu

  • 出版商: Wiley
  • 出版日期: 2004-02-19
  • 售價: $3,730
  • 貴賓價: 9.5$3,544
  • 語言: 英文
  • 頁數: 207
  • 裝訂: Hardcover
  • ISBN: 0471657204
  • ISBN-13: 9780471657200
  • 相關分類: VLSI
  • 下單後立即進貨 (約1~3週)




A hands-on troubleshooting guide for VLSI network designers
The primary goal in VLSI (very large scale integration) power network design is to provide enough power lines across a chip to reduce voltage drops from the power pads to the center of the chip. Voltage drops caused by the power network's metal lines coupled with transistor switching currents on the chip cause power supply noises that can affect circuit timing and performance, thus providing a constant challenge for designers of high-performance chips.
Power Distribution Network Design for VLSI provides detailed information on this critical component of circuit design and physical integration for high-speed chips. A vital tool for professional engineers (especially those involved in the use of commercial tools), as well as graduate students of engineering, the text explains the design issues, guidelines, and CAD tools for the power distribution of the VLSI chip and package, and provides numerous examples for its effective application.
Features of the text include:
* An introduction to power distribution network design
* Design perspectives, such as power network planning, layout specifications, decoupling capacitance insertion, modeling, and analysis
* Electromigration phenomena
* IR drop analysis methodology
* Commands and user interfaces of the VoltageStorm(TM) CAD tool
* Microprocessor design examples using on-chip power distribution
* Flip-chip and package design issues
* Power network measurement techniques from real silicon
The author includes several case studies and a glossary of key words and basic terms to help readers understand and integrate basic concepts in VLSI design and power distribution.


Table of Contents:


1 Introduction.

1.1 Power Supply Noise.

1.2 Power Network Modeling.

1.3 Modelling of Switching Currents.

1.4 On-Chip Decoupling Capacitance.

1.5 On-Chip Inductance.

1.6 Process Scaling Impacts.

1.7 Summary.

2 Design Perspectives.

2.1 Planning for Communication Chips.

2.2 Planning for Microprocessor Chips.

2.3 IBM CAD Methodology.

2.4 Design for IR Drop.

2.5 Package-Level Methodology.

2.6 Summary.

3 Electromigration.

3.1 Basic Definitions and EM Rules.

3.2 EM Analysis Tool.

3.3 Full-Chip EM Methodology.

3.4 Summary.

4 IR Voltage Drop.

4.1 Causes of IR Drop.

4.2 Overview of IR Analysis.

4.3 Static Analysis Approach.

4.4 Dynamic Analysis Approach.

4.5 Circuit Analysis with IR Drop Impacts.

4.6 Summary.

5 Power Grid Analysis.

5.1 Introduction.

5.2 Executing the Tool.

5.3 Advanced Static Analysis.

5.4 Dynamic Analysis.

5.5 Layout Exploration.

5.6 Summary.

6 Microprocessor Design Examples.

6.1 Intel IA-32 Pentium-III.

6.2 Sun UltraSPARC.

6.3 Hitachi SuperH Microprocessor.

6.4 IBM S/390 Microprocessor.

6.5 Sun SPARC 64b Microprocessor.

6.6 Intel IA-64 Microprocessor.

6.7 Summary.

7 Package and I/O Design for Power Delivery.

7.1 Flip-Chip Package.

7.2 Simultaneous Switching Noise (SSN).

7.3 Case Study of a Microprocessor-Like Chip.

7.4 Power Supply Measurement.

7.5 I/O Pads for Power/Ground Supplies.