Energy Efficient and Reliable Embedded Nanoscale SRAM Design
暫譯: 高效能與可靠的嵌入式奈米級SRAM設計

本參考文本涵蓋了設計穩健的嵌入式記憶體和周邊電路的廣泛範疇。它將成為電子與通信工程、電機工程、機械工程以及航空航天工程等領域的高年級本科生、研究生和專業人士的有用教材。

Bhupendra Singh Reniwal received B. Tech & M. Tech from SGSITS-Indore and Ph.D. from IIT, Indore, India in 2006, 2011 and 2016 respectively. He is currently working as Assistant Professor in the Department of Electrical Engineering, Indian Institute of Technology Jodhpur, India. Post Ph.D. he has worked as a Senior Product Development Engineer, Semiconductor Vertical in UST Global Bangalore, India Mixed-Signal IP Solution Group (MIG) at Intel Corporation Penang, Malaysia, and Systems & Technology Group, ASIC Foundry, IBM Bangalore where he was involved on developing Energy Efficient Memory Architecture, I/O Circuit Design, and its pre-silicon validation, for Internet of Things (IoT), applications in subnanometric trigate FinFET processes. In IBM he was involved in R&D on low power methodology definition at Schematic2GDS level for sub-nanometric nodes, especially for FinFET memory design. He has served the Department of Electronics & Communication Engineering IIITDM Kancheepuram and BITS Pilani, as an Assistant Professor from Nov-2019 to Oct-2022 and May-Dec 2017, respectively. He is a recipient of the prestigious SIRE-2022 Faculty Fellowship from the Department of Science & Technology (DST) GOI and joined University of Virginia, USA as a Visiting Faculty. He received the User Design Best Research Paper Award in IEEE 29th International Conference on VLSI Design and Best Poster Presentation Award for Ultra Low Power SRAM Design in Ramanujan Conclave 2016. He is a recipient of the International Travel Award as early recognition in Solid State Circuit Design from the Association of Computing Machinery (ACM), NY, USA, and DST.

Dr. Pooran Singh is an Assistant Professor in the Department of Electrical and Computer Engineering at Mahindra University École Centrale School of Engineering. Dr. Pooran graduated with a Ph.D. from the Department of Electrical Engineering, IIT Indore. He is a Fulbright-Nehru Doctoral Fellow (2014-15). Under Fulbright Fellowship he was associated with the Department Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta USA for a period of one year. Prior to joining MU, he was an Analog Design Engineer (SRAM Design) at Intel Microelectronics, Penang, Malaysia. Over there his his primary work included designing SRAM circuits, Pre-layout SRAM design and analysis of its various design parameters i.e. read margin/write margin, critical path, read/write performance, dynamic and leakage power at different PVT values for Intel's 7nm and 10nm FPGAs. His primary research work includes designing low power and robust SRAM for space applications, In-Memory compute and for IoT devices.

Dr. Ambika Prasad Shah is currently working as an Assistant Professor, Electrical Engineering Department, and Associate Dean Corporate Relations at Indian Institute of Technology Jammu, India. He received Ph.D. degree from the Electrical Engineering Department, Indian Institute of Technology Indore, India. Before joining IIT Jammu, Dr. Shah worked as a Postdoctoral Fellow at the Institute for Microelectronics, TU Vienna, Austria. He is the recipient of the Young Scientist Award from the M.P. Council of Science and Technology Bhopal, M.P. India. He has authored/co-authored more than 70 research papers in peer-reviewed international journals and conferences. He was the Conference Organizing Chair for VDAT-2022 and Fellowship Chair for VLSID-2022. He is a fellow of IETE, senior member of IEEE, and member of ACM, ISTE, ISCA, IEI, and IAENG.

His current research interest includes reliability analysis of digital circuits, Design for reliability, fault-tolerant circuits, reliability modeling, low power high-performance circuit designs, and Hardware Security circuits.

Prof. Santosh Kumar Vishvakarma is with the Department of Electrical Engineering, Indian Institute of Technology Indore, MP, India as Professor. He is engaged with teaching and research in the area of Energy-Efficient and Reliable SRAM Memory Design, Enhancing Performance and Configurable Architecture for DNN Accelerators, SRAM based In-Memory Computing Architecture for Edge AI, Reliable, Secure Design for IoT Application, Design for Reliability. Prof. Vishvakarma is the reviewer of various Journals like IEEE Transaction on Electron Devices, IEEE Transaction on Nanotechnology, IEEE Transaction on VLSI Integration System, Elsevier Microelectronics Journal, Elsevier Integration the VLSI Journal, IEEE Transaction on VLSI Integration System, Analog Integrated Circuits and Signal Processing Springer, Circuits, Systems & Signal Processing (CSSP), Solid State Electronics etc. He is a Member of IEEE, Professional Member of VLSI Society of India, Associate Member of Institute of Nanotechnology, Life member of Indian Microelectronics Society (IMS), India.

He is the General Chair of 23rd International Symposium on VLSI Design and Test (VDAT-2019) On July 4-6, 2019, IIT Indore, India.

Prof. Vishvakarma did schooling from Gorakhpur itself and then Bachelor of Science (B.Sc.) in Electronics, Master of Science (M.Sc.) in Electronics and Master of Technology (M.Tech.) in Microelectronics from University of Gorakhpur, Devi Ahilya Vishvidayalaya Indore and Panjab University Chandigarh in 1999, 2001 and 2003 respectively. Dr. Vishvakarma obtained Ph.D. degree on the topic "Analytical Modeling of Low Leakage MGDG MOSFET and its Application to SRAM" from Microelectronics and VLSI Group, Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee (IITR) in 2010 and worked under the supervision of Prof. S. Dasgupta, & Prof. A. K. Saxena in the area of MOS device modeling and SRAM circuit design.

Bhupendra Singh Reniwal於2006年、2011年和2016年分別在SGSITS-Indore獲得B. Tech和M. Tech學位，並在印度IIT Indore獲得博士學位。他目前在印度喬德布爾的印度理工學院電機工程系擔任助理教授。博士後，他曾在UST Global Bangalore擔任高級產品開發工程師，並在Intel Corporation Penang的混合信號IP解決方案小組（MIG）和IBM Bangalore的系統與技術小組、ASIC鑄造部門工作，參與開發針對物聯網（IoT）應用的能效記憶體架構、I/O電路設計及其前矽驗證，使用亞奈米三閘極FinFET工藝。在IBM，他參與了針對亞奈米節點的低功耗方法學定義的研究與開發，特別是針對FinFET記憶體設計。他曾於2019年11月至2022年10月及2017年5月至12月擔任IIITDM Kancheepuram和BITS Pilani的電子與通信工程系助理教授。他是印度科學與技術部（DST）頒發的SIRE-2022教職員獎學金的獲得者，並作為訪問教員加入美國維吉尼亞大學。他在IEEE第29屆國際VLSI設計會議中獲得用戶設計最佳研究論文獎，並在2016年Ramanujan Conclave中獲得超低功耗SRAM設計最佳海報展示獎。他還獲得了計算機協會（ACM）和DST頒發的國際旅行獎，以表彰他在固態電路設計方面的早期成就。

Dr. Pooran Singh是馬欣德拉大學École Centrale工程學院電機與計算機工程系的助理教授。Dr. Pooran在印度IIT Indore的電機工程系獲得博士學位。他是Fulbright-Nehru博士獎學金獲得者（2014-15）。在Fulbright獎學金的支持下，他曾在美國喬治亞理工學院的電機與計算機工程系工作一年。在加入MU之前，他曾在馬來西亞Penang的Intel微電子公司擔任類比設計工程師（SRAM設計）。在那裡，他的主要工作包括設計SRAM電路、前佈局SRAM設計及其各種設計參數的分析，即讀取裕度/寫入裕度、關鍵路徑、讀取/寫入性能、不同PVT值下的動態和漏電功率，針對Intel的7nm和10nm FPGA。他的主要研究工作包括為太空應用、內存計算和物聯網設備設計低功耗和穩健的SRAM。

Dr. Ambika Prasad Shah目前在印度喬木爾的印度理工學院電機工程系擔任助理教授及企業關係副院長。他在印度IIT Indore的電機工程系獲得博士學位。在加入IIT Jammu之前，Dr. Shah曾在奧地利維也納的微電子研究所擔任博士後研究員。他是印度M.P.科學與技術委員會頒發的青年科學家獎的獲得者。他在同行評審的國際期刊和會議上發表了70多篇研究論文。他曾擔任VDAT-2022的會議組織主席和VLSID-2022的獎學金主席。他是IETE的會員，IEEE的高級會員，以及ACM、ISTE、ISCA、IEI和IAENG的會員。

他目前的研究興趣包括數位電路的可靠性分析、可靠性設計、容錯電路、可靠性建模、低功耗高性能電路設計和硬體安全電路。

Prof. Santosh Kumar Vishvakarma是印度IIT Indore電機工程系的教授。他專注於能效和可靠的SRAM記憶體設計、增強性能和可配置架構的DNN加速器、基於SRAM的邊緣AI內存計算架構、物聯網應用的可靠安全設計及可靠性設計的教學和研究。Prof. Vishvakarma是多個期刊的審稿人，如IEEE電子設備交易、IEEE納米技術交易、IEEE VLSI整合系統交易、Elsevier微電子期刊、Elsevier VLSI整合期刊、IEEE VLSI整合系統交易、類比集成電路與信號處理（Springer）、電路、系統與信號處理（CSSP）、固態電子學等。他是IEEE的會員，印度VLSI協會的專業會員，納米技術研究所的副會員，以及印度微電子學會（IMS）的終身會員。

他是第23屆國際VLSI設計與測試研討會（VDAT-2019）的總主席，會議於2019年7月4日至6日在印度IIT Indore舉行。

Prof. Vishvakarma在戈拉克布爾完成學業，並於1999年獲得電子學學士（B.Sc.）、2001年獲得電子學碩士（M.Sc.）及2003年獲得微電子學碩士（M.Tech.）學位，分別來自戈拉克布爾大學、德維阿希利亞大學Indore和昌迪加爾的旁遮普大學。Dr. Vishvakarma於2010年在印度羅爾基的印度理工學院（IITR）電子與計算機工程系的微電子與VLSI小組獲得博士學位，研究主題為「低漏電MGDG MOSFET的分析建模及其在SRAM中的應用」，並在MOS器件建模和SRAM電路設計領域在Prof. S. Dasgupta和Prof. A. K. Saxena的指導下進行研究。