Vertical 3D Memory Technologies (Hardcover)

The large scale integration and planar scaling of individual system chips is reaching an expensive limit. If individual chips now, and later terrabyte memory blocks, memory macros, and processing cores, can be tightly linked in optimally designed and processed small footprint vertical stacks, then performance can be increased, power reduced and cost contained. This book reviews for the electronics industry engineer, professional and student the critical areas of development for 3D vertical memory chips including: gate-all-around and junction-less nanowire memories, stacked thin film and double gate memories,  terrabit vertical channel and vertical gate stacked NAND flash, large scale stacking of  Resistance RAM cross-point arrays, and 2.5D/3D stacking of memory and processor chips with through-silicon-via  connections now and remote links later.

Key features:

• Presents a review of the status and trends in 3-dimensional vertical memory chip technologies.
• Extensively reviews advanced vertical memory chip technology and development
• Explores technology process routes and 3D chip integration in a single reference

大規模整合和平面縮放個別系統晶片已達到昂貴的極限。如果個別晶片現在，以及後來的TB記憶塊、記憶宏和處理核心，可以在最佳設計和處理的小尺寸垂直堆疊中緊密連接，那麼性能可以提高，功耗可以降低，成本可以控制。本書對於電子行業的工程師、專業人士和學生，回顧了3D垂直記憶晶片發展的關鍵領域，包括：全閘極和無接面奈米線記憶體、堆疊薄膜和雙閘極記憶體、TB垂直通道和垂直閘極堆疊NAND快閃記憶體、大規模堆疊的阻抗RAM交叉點陣列，以及現在和以後通過矽通孔連接的記憶體和處理器晶片的2.5D/3D堆疊。

主要特點：
- 提供了3D垂直記憶晶片技術的現狀和趨勢評論。
- 廣泛評論了先進的垂直記憶晶片技術和發展。
- 探討了技術過程路線和3D晶片集成的單一參考資料。