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商品描述
The large scale integration and planar scaling of individual system chips is reaching an expensive limit. If individual chips now, and later terrabyte memory blocks, memory macros, and processing cores, can be tightly linked in optimally designed and processed small footprint vertical stacks, then performance can be increased, power reduced and cost contained. This book reviews for the electronics industry engineer, professional and student the critical areas of development for 3D vertical memory chips including: gate-all-around and junction-less nanowire memories, stacked thin film and double gate memories, terrabit vertical channel and vertical gate stacked NAND flash, large scale stacking of Resistance RAM cross-point arrays, and 2.5D/3D stacking of memory and processor chips with through-silicon-via connections now and remote links later.
Key features:
- Presents a review of the status and trends in 3-dimensional vertical memory chip technologies.
- Extensively reviews advanced vertical memory chip technology and development
- Explores technology process routes and 3D chip integration in a single reference
商品描述(中文翻譯)
大型集成和單一系統晶片的平面縮放已達到昂貴的極限。如果現在的單一晶片，以及未來的太字節記憶體模塊、記憶體宏和處理核心，能夠在最佳設計和處理的小型垂直堆疊中緊密連接，那麼性能可以提高，功耗可以降低，成本也能得到控制。本書針對電子產業的工程師、專業人士和學生，回顧了3D垂直記憶體晶片的關鍵發展領域，包括：全圍閘（gate-all-around）和無接面（junction-less）奈米線記憶體、堆疊薄膜和雙閘記憶體、太位元垂直通道和垂直閘堆疊的NAND閃存、大規模堆疊的電阻式隨機存取記憶體（Resistance RAM）交叉點陣列，以及記憶體和處理器晶片的2.5D/3D堆疊，並透過矽通孔（through-silicon-via）連接，未來還將有遠端連結。
主要特點：
- 提供3維垂直記憶體晶片技術的現狀和趨勢回顧。
- 廣泛回顧先進的垂直記憶體晶片技術和發展。
- 探討技術流程路徑和3D晶片整合的單一參考。
