Network-on-Chip: The Next Generation of System-on-Chip Integration

Addresses the Challenges Associated with System-on-Chip Integration

Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends.

Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design.

This text comprises 12 chapters and covers:

• The evolution of NoC from SoC―its research and developmental challenges
• NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces
• The router design strategies followed in NoCs
• The evaluation mechanism of NoC architectures
• The application mapping strategies followed in NoCs
• Low-power design techniques specifically followed in NoCs
• The signal integrity and reliability issues of NoC
• The details of NoC testing strategies reported so far
• The problem of synthesizing application-specific NoCs
• Reconfigurable NoC design issues
• Direction of future research and development in the field of NoC

Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems.

「應對片上系統整合所面臨的挑戰」

「網路晶片：下一代片上系統整合」探討了限制晶片間通訊效率的當前問題，並探索了網路晶片（NoC）作為一種有前景的替代方案，它使設計師能夠在單一片上系統（SoC）上集成大量核心，從而產生可擴展、可重用和高性能的通訊骨幹。本書提供了與基於NoC的設計相關的基本概述：通訊基礎設施設計、通訊方法論、評估框架以及應用映射到NoC上。它詳細介紹了不同提出的NoC結構的設計和評估、低功耗技術、信號完整性和可靠性問題、應用映射、測試和未來趨勢。

通過使用在工業和學術界實施的芯片的示例，本書展示了在工業CAD工具中驗證的組件的完整架構設計。它描述了NoC的研究和發展，包括加強分析程序的理論證明，以及NoC設計和合成中使用的算法。此外，它還考慮了其他即將出現的NoC問題，如低功耗NoC設計、信號完整性問題、NoC測試、重構、合成和三維NoC設計。

本書共有12章，涵蓋了以下內容：
- NoC從SoC演變的研究和發展挑戰
- NoC協議，包括流量控制、可用的網路拓撲、路由機制、容錯能力、服務質量支持和網路接口設計
- NoC中的路由器設計策略
- NoC架構的評估機制
- NoC中的應用映射策略
- NoC中特定的低功耗設計技術
- NoC的信號完整性和可靠性問題
- 迄今為止報告的NoC測試策略
- 應用特定NoC的合成問題
- 可重構NoC設計問題
- NoC領域未來研究和發展的方向

「網路晶片：下一代片上系統整合」涵蓋了與基於NoC的設計相關的基本主題、技術和未來趨勢，適用於對計算機架構、嵌入式系統和並行/分佈式系統感興趣的工程師、學生、研究人員和其他行業專業人士使用。