Compact Models for Integrated Circuit Design: Conventional Transistors and Beyond

Compact Models for Integrated Circuit Design: Conventional Transistors and Beyond provides a modern treatise on compact models for circuit computer-aided design (CAD). Written by an author with more than 25 years of industry experience in semiconductor processes, devices, and circuit CAD, and more than 10 years of academic experience in teaching compact modeling courses, this first-of-its-kind book on compact SPICE models for very-large-scale-integrated (VLSI) chip design offers a balanced presentation of compact modeling crucial for addressing current modeling challenges and understanding new models for emerging devices.

Starting from basic semiconductor physics and covering state-of-the-art device regimes from conventional micron to nanometer, this text:

• Presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models
• Discusses the major issue of process variability, which severely impacts device and circuit performance in advanced technologies and requires statistical compact models
• Promotes further research of the evolution and development of compact models for VLSI circuit design and analysis
• Supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices
• Includes exercise problems at the end of each chapter and extensive references at the end of the book

Compact Models for Integrated Circuit Design: Conventional Transistors and Beyond is intended for senior undergraduate and graduate courses in electrical and electronics engineering as well as for researchers and practitioners working in the area of electron devices. However, even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts from this book.

《集成電路設計的緊湊模型：傳統晶體管及其延伸》提供了一本關於電路計算機輔助設計（CAD）中緊湊模型的現代論述。本書作者在半導體工藝、器件和電路CAD方面擁有超過25年的行業經驗，以及在教授緊湊建模課程方面擁有超過10年的學術經驗。這本關於非常大規模集成（VLSI）芯片設計的緊湊SPICE模型的首部著作，提供了平衡的簡介，關鍵是緊湊建模，以應對當前建模挑戰並理解新興器件的新模型。

本書從基本的半導體物理學開始，涵蓋了從傳統微米到納米的最新器件狀態，內容包括：

- 提供了行業標準的雙極晶體管（BJTs）、金屬-氧化物-半導體（MOS）場效應晶體管（FETs）、FinFETs和隧道場效應晶體管（TFETs）的模型，以及統計MOS模型。
- 討論了嚴重影響先進技術中器件和電路性能的工藝變異性的主要問題，需要統計緊湊模型。
- 促進了對VLSI電路設計和分析的緊湊模型演變和發展的進一步研究。
- 提供了使用納米尺度器件進行高效集成電路（IC）設計所需的基礎和實用知識。
- 每章末尾提供練習問題，書末提供廣泛的參考文獻。

《集成電路設計的緊湊模型：傳統晶體管及其延伸》適用於電氣和電子工程的高年級本科和研究生課程，以及在電子器件領域工作的研究人員和從業人員。然而，即使對半導體物理學不熟悉的讀者也可以從本書中獲得緊湊建模概念的扎實理解。

Samar K. Saha holds a Ph.D from Gauhati University, and an M.S.EM from Stanford University. He is currently adjunct professor at Santa Clara University, technical advisor at Ultrasolar Technology, distinguished lecturer and 2016-2017 president of the IEEE Electron Devices Society, and fellow of the Institution of Engineering and Technology. He previously worked for National Semiconductor, LSI Logic, Texas Instruments, Philips Semiconductors, Silicon Storage Technology, Synopsys, DSM Solutions, Silterra USA, and SuVolta, and served as a faculty member at Southern Illinois University at Carbondale, Auburn University, University of Nevada at Las Vegas, and the University of Colorado at Colorado Springs.

Samar K. Saha擁有Gauhati大學的博士學位和Stanford大學的M.S.EM學位。他目前是Santa Clara大學的兼職教授，Ultrasolar Technology的技術顧問，IEEE Electron Devices Society的傑出講師和2016-2017年的主席，以及工程與技術學會的會士。他曾在National Semiconductor、LSI Logic、Texas Instruments、Philips Semiconductors、Silicon Storage Technology、Synopsys、DSM Solutions、Silterra USA和SuVolta工作，並在Southern Illinois University at Carbondale、Auburn University、University of Nevada at Las Vegas和University of Colorado at Colorado Springs擔任教職。