Circuit Techniques for Low-Voltage and High-Speed A/d Converters (Hardcover)
暫譯: 低電壓與高速A/D轉換器的電路技術 (精裝版)

Mikko E. Waltari, Kari A.I. Halonen

Circuit Techniques for Low-Voltage and High-Speed A/d Converters (Hardcover)
  • 出版商: Kluwer Academic Publ
  • 出版日期: 2002-10-31
  • 售價: $830
  • 貴賓價: 9.8 折 $813
  • 語言: 英文
  • 頁數: 254
  • 裝訂: Hardcover
  • ISBN: 1402072449
  • ISBN-13: 9781402072444
  • 相關分類: 電路學 Electric-circuits

    • 下單後立即進貨 (約5~7天)

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商品描述

The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage. Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented. It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes. An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering. The throughput of ADCs can be increased by using parallelism. This is demonstrated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. Circuit Techniques for Low-Voltage and High-Speed A/D Converters presents a total of seven prototypes: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO techniques. This monograph will prove to be a useful reference for both academics and professionals whom are active in the Analog Circuit Design and Communications field.

商品描述(中文翻譯)

隨著電子應用領域的數位化日益增加，從電信系統到消費電子產品，對於模擬轉數位轉換器（ADC）的需求也隨之提升，要求其具備更高的取樣率、更高的解析度以及更低的功耗。集成電路技術的演進在某種程度上有助於滿足這些需求，透過提供更快的設備並實現更複雜的功能於特定的矽區域，但同時也帶來了新的挑戰，其中最重要的是供應電壓的降低。基於開關電容（SC）技術，管線架構最成功地利用了CMOS技術的特性來實現高速高解析度的ADC。對供應電壓和技術縮放對SC電路影響的分析顯示，至少在接下來的幾個技術世代中，可以期待其帶來的好處。運算放大器是SC電路中的核心構建塊，因此對不同拓撲及其低電壓能力進行了比較。眾所周知，標準形式的SC技術不適用於非常低的供應電壓，主要是因為開關控制電壓不足。研究了兩種低電壓的修改方案：開關引導（switch bootstrapping）和開關運算放大器（SO）技術。為這兩種方案提出了改進的電路結構。展示了兩個使用SO技術的ADC原型，同時在另外三個原型中使用了引導開關。ADC的一個重要組成部分是前端取樣保持（S/H）電路。在高信號頻率下，其線性度主要由所使用的開關決定。對S/H架構進行了回顧，並研究了通過引導技術進行開關線性化的應用，並將其應用於兩個原型中。另一個重要參數是取樣時鐘抖動，對其進行了分析，並通過精心設計的時鐘生成和緩衝來最小化。通過使用並行性，可以提高ADC的吞吐量。這在電路層面上通過雙重取樣技術得以展示，該技術應用於S/H電路和管線ADC。對雙重取樣中的非理想性進行了分析。在系統層面上，並行性被應用於時間交錯ADC。並行信號路徑的失配會產生錯誤，為消除這些錯誤，開發了一種對時間偏移不敏感的取樣電路和數位偏移校準。低電壓和高速A/D轉換器的電路技術展示了總共七個原型：兩個雙重取樣的S/H電路、一個時間交錯ADC、一個IF取樣自校準的管線ADC、一個帶去毛刺器的電流引導DAC，以及兩個採用SO技術的管線ADC。這本專著將成為活躍於模擬電路設計和通訊領域的學術界和專業人士的有用參考資料。

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