Low-Voltage CMOS Log Companding Analog Design

Description

Low-Voltage CMOS Log Companding Analog Design presents in detail state-of-the-art analog circuit techniques for the very low-voltage and low-power design of systems-on-chip in CMOS technologies. The proposed strategy is mainly based on two bases: the Instantaneous Log Companding Theory, and the MOSFET operating in the subthreshold region. The former allows inner compression of the voltage dynamic-range for very low-voltage operation, while the latter is compatible with CMOS technologies and suitable for low-power circuits. The required background on the specific modeling of the MOS transistor for Companding is supplied at the beginning. Following this general approach, a complete set of CMOS basic building blocks is proposed and analyzed for a wide variety of analog signal processing. In particular, the covered areas include: amplification and AGC, arbitrary filtering, PTAT generation, and pulse duration modulation (PDM). For each topic, several case studies are considered to illustrate the design methodology. Also, integrated examples in 1.2um and 0.35um CMOS technologies are reported to verify the good agreement between design equations and experimental data. The resulting analog circuit topologies exhibit very low-voltage (i.e. 1V) and low-power (few tenths of uA) capabilities. Apart from these specific design examples, a real industrial application in the field of hearing aids is also presented as the main demonstrator of all the proposed basic building blocks. This system-on-chip exhibits true 1V operation, high flexibility through digital programmability and very low-power consumption (about 300uA including the Class-D amplifier). As a result, the reported ASIC can meet the specifications of a complete family of common hearing aid models. In conclusion, this book is addressed to both industry ASIC designers who can apply its contents to the synthesis of very low-power systems-on-chip in standard CMOS technologies, as well as to the teachers of modern circuit design in electronic engineering.

《低壓CMOS對數壓縮類比設計》詳細介紹了CMOS技術下系統單晶片的低壓低功耗類比電路技術。該書主要基於兩個基礎：瞬時對數壓縮理論和在亞臨界區域工作的MOSFET。前者允許在非常低電壓操作下對電壓動態範圍進行內部壓縮，而後者與CMOS技術兼容且適用於低功耗電路。書中首先提供了有關對數壓縮的MOS晶體管特定建模的必要背景知識。在這一整體方法的基礎上，提出並分析了一套完整的CMOS基本構建塊，適用於各種類比信號處理，包括放大和自動增益控制、任意濾波、PTAT生成和脈衝持續調變（PDM）。對於每個主題，考慮了多個案例研究以說明設計方法。此外，還報告了在1.2um和0.35um CMOS技術下的集成示例，以驗證設計方程和實驗數據之間的良好一致性。所得到的類比電路拓撲具有非常低的電壓（即1V）和低功耗（幾十微安）能力。除了這些具體的設計示例外，還介紹了聽力輔助器領域的一個真實工業應用作為所有提出的基本構建塊的主要演示器。該系統單晶片實現了真正的1V操作，通過數字可編程實現高靈活性，並具有非常低的功耗（包括類D放大器在內約300微安）。因此，該報告的ASIC可以滿足完整系列常見聽力輔助器型號的規格要求。總之，本書既適用於能夠將其內容應用於標準CMOS技術下非常低功耗系統單晶片的行業ASIC設計師，也適用於電子工程中現代電路設計的教師。