Mixed-Signal Layout Generation Concepts

Chieh Lin, Arthur H.M. van Roermund, Domine Leenaerts

  • 出版商: Springer
  • 出版日期: 2003-10-31
  • 售價: $1,600
  • 貴賓價: 9.8$1,568
  • 語言: 英文
  • 頁數: 210
  • 裝訂: Hardcover
  • ISBN: 1402075987
  • ISBN-13: 9781402075988
  • 下單後立即進貨 (約5~7天)





Mixed-Signal Layout Generation Concepts covers important physical-design issues that exist in contemporary analog and mixed-signal design flows. Due to the increasing pressure on time-to-market, the steep increase in chip fabrication costs, and the increasing design complexity, it becomes even more challenging to produce a first-time right IC layout. The fundamental issues in creating a layout are placement and routing. Although these coupled problems have been investigated for many decades, no satisfactory automated solution has emerged yet. Fortunately, supported by modern computing power and results of new research that further improve computation efficiency, significant steps forward have been taken.
Mixed-Signal Layout Generation Concepts brings together many principles and techniques required to successfully develop and implement layout generation tools to accommodate many mixed-signal layout generation needs. Not only does it provide a comprehensive overview of state-of-the-art concepts, it also illustrates many concepts with intuitive examples and pseudo code. Altogether, it facilitates creation of insight in a vast and complex area.
For those who are new to the area of mixed-signal layout generation, this book provides an excellent introduction to advanced topics in this area. A practicing EDA researcher or tool developer might find this book a useful reference that combines classical and new principles. In addition, this book relates theories to each other and to pragmatic implementations. Finally, the designer, or layout artist, interested to have a thorough understanding of fundamental concepts in mixed-signal layout generation, can take advantage of the self-contained chapters in this book.
Table of contents

Preface. List of Abbreviations.
1: Introduction. 1.1. Outline of the Book.
2: Mapping Problems in the Design Flow. 2.1. Top-Down Flow and Bottom-Up Approach. 2.2. The Mapping Problem. 2.3. Placement and Routing Constraints.
3: Optimization Methods. 3.1. VLSI Optimization Methods. 3.2. Simulated Annealing. 3.3. Concluding Remarks.
4: Optimization Approach Based on Simulated Annealing. 4.1. Optimization Flow. 4.2. Problem Representation. 4.3. Perturbation Operators. 4.4. Acceptance and Generation Functions. 4.5. Temperature Schedule. 4.6. Stop Criterion. 4.7. Cost Function. 4.8. Concluding Remarks.
5: Efficient Algorithms and Data Structures. 5.1. Computational Model. 5.2. Asymptotic Analysis. 5.3. Computational Complexity. 5.4. Data Structures for CAD. 5.5. Concluding Remarks.
6: Placement. 6.1. Previous Work. 6.2. Effective and Efficient Placement. 6.3. Representation Generality, Flexibility and Sensitivity. 6.4. Sequence Pair Representation. 6.5. Graph-Based Packing Computation. 6.6.Non-Graph-Based Packing Computation. 6.7. Graph-Based Incremental Placement Computation. 6.8. Implementation Considerations. 6.9. Experimental Results. 6.10. Placement-to-Sequence-Pair Mapping. 6.11.Constrained Block Placement. 6.12. Concluding Remarks. 7: Routing. 7.1. The Routing Problem. 7.2. Classification of Routing Approaches. 7.3. Previous Work. 7.4. Computational Complexity. 7.5. Global Routing Model. 7.6. Global Routing Algorithms. 7.7. Benchmarking of Heuristics in Our Routing Model. 7.8. Incremental Routing. 7.9. Impact of Routing on Placement Quality. 7.10. Concluding Remarks.
8: Dealing with Physical Phenomena: Parasitics, Crosstalk and Process Variations. 8.1. Previous Work. 8.3. Self-Parasitics. 8.4. Crosstalk. 8.5. Process Variations. 8.6. Incorporating Crosstalk and Parasitics into Routing. 8.7. Incorporating Substrate Coupling into Placement. 8.8. Incremental Substrate Coupling Impact Minimization. 8.9. Concluding Remarks.
9: Conclusions. Bibliography. About the Authors. Index.