Low Power Analog CMOS for Cardiac Pacemakers: Design and Optimization in Bulk and SOI Technologies (Hardcover)

Fernando Silveira, Denis Flandre

  • 出版商: Springer
  • 出版日期: 2004-01-31
  • 售價: $1,600
  • 貴賓價: 9.8$1,568
  • 語言: 英文
  • 頁數: 208
  • 裝訂: Hardcover
  • ISBN: 140207719X
  • ISBN-13: 9781402077197
  • 相關分類: CMOSMaker
  • 下單後立即進貨 (約5~7天)

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Description

Power reduction is a central priority in battery-powered medical implantable devices, particularly pacemakers, to either increase battery lifetime or decrease size using a smaller battery. Low Power Analog CMOS for Cardiac Pacemakers proposes new techniques for the reduction of power consumption in analog integrated circuits. Our main example is the pacemaker sense channel, which is representative of a broader class of biomedical circuits aimed at qualitatively detecting biological signals.

The first and second chapters are a tutorial presentation on implantable medical devices and pacemakers from the circuit designer point of view. This is illustrated by the requirements and solutions applied in our implementation of an industrial IC for pacemakers. There from, the book discusses the means for reduction of power consumption at three levels: base technology, power-oriented analytical synthesis procedures and circuit architecture.

At the technology level, we analyze the impact that the application of the fully depleted silicon-on-insulator (FD SOI) technology has on this kind of analog circuits. The basic building block levels as well as the system level (pacemaker sense channel) are considered. Concerning the design technique, we apply a methodology, based on the transconductance to current ratio that exploits all regions of inversion of the MOS transistor. Various performance aspects of analog building blocks are modeled and a power optimization synthesis of OTAs for a given total settling time (including the slewing and linear regions) is proposed.

At the circuit level, we present a new design approach of a class AB output stage suitable for micropower application. In our design approach, the usual advantages of the application of a class AB output stage are enhanced by the application of a transconductance multiplication effect. These techniques are tested in experimental prototypes of amplifiers and complete pacemaker sense channel implementations in SOI and standard bulk CMOS technologies. An ultra low consumption of 110 nA (0.3µ W) is achieved in a FD SOI sense channel implementation.

Though primarily addressed to the pacemaker system, the techniques proposed are shown to have application in other contexts where power reduction is a main concern.

Table of contents
Acknowledgements. Preface.
1. Implantable Cardiac Pacemakers.
2. Industrial Implementation of Pacemaker Integrated Circuit in Bulk CMOS Technology.

3. Potential of SOI Technology for Low-Voltage Micropower Biomedical Applications.
4. Power Optimization in Operational Amplifier Design.
5. Class AB Micropower Operations Amplifiers.
6. Implementation of Pacemaker Sense Circuits.
Appendix 1: Integration of Large Time Constants.
Appendix 2: Design of Accelerometer Signal Conditioning Circuit of Industrial Pacemaker IC in Bulk CMOS Technology.
Bibliography. Index.

商品描述(中文翻譯)

描述

降低功耗是電池供電的醫療植入式設備,特別是心臟起搏器中的一個核心優先事項,可以增加電池壽命或使用更小的電池減小尺寸。《心臟起搏器的低功耗模擬CMOS》提出了降低模擬集成電路功耗的新技術。我們的主要示例是起搏器感測通道,它代表了一個更廣泛的生物醫學電路類別,旨在定性檢測生物信號。

第一章和第二章是從電路設計師的角度對植入式醫療設備和心臟起搏器的教程介紹。這是通過我們在心臟起搏器工業集成電路實現中應用的要求和解決方案來說明的。從那裡開始,本書討論了在三個層面上降低功耗的手段:基礎技術、以功耗為導向的分析合成程序和電路架構。

在技術層面上,我們分析了全耗盡絕緣體上硅(FD SOI)技術對這類模擬電路的影響。考慮了基本的構建塊級別以及系統級別(起搏器感測通道)。關於設計技術,我們應用了一種基於跨導到電流比的方法,該方法利用了MOS晶體管的所有反轉區域。對模擬構建塊的各種性能方面進行建模,並提出了根據給定的總定位時間(包括斜升和線性區域)對OTA進行功耗優化合成的方法。

在電路層面上,我們提出了一種適用於微功率應用的AB類輸出級的新設計方法。在我們的設計方法中,通過應用跨導倍增效應增強了應用AB類輸出級的通常優勢。這些技術在SOI和標準堆積CMOS技術的放大器和完整的起搏器感測通道實現的實驗原型中進行了測試。在FD SOI感測通道實現中實現了超低的110 nA(0.3微瓦)功耗。

儘管主要針對起搏器系統,但所提出的技術在其他關注功耗降低的情境中也有應用。

目錄

致謝。前言。
1. 植入式心臟起搏器。
2. 心臟起搏器集成電路在堆積CMOS技術中的工業實現。
3. SOI技術在低壓微功率生物醫學應用中的潛力。
4. 運算放大器設計中的功耗優化。
5. AB類微功率運算放大器。
6. 起搏器感測電路的實現。
附錄1:大時間常數的集成。
附錄2:工業起搏器加速度計信號調節電路的設計。