VLSI Architectures for Modern Error-Correcting Codes

Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity.

VLSI Architectures for Modern Error-Correcting Codes serves as a bridge connecting advancements in coding theory to practical hardware implementations. Instead of focusing on circuit-level design techniques, the book highlights integrated algorithmic and architectural transformations that lead to great improvements on throughput, silicon area requirement, and/or power consumption in the hardware implementation.

The goal of this book is to provide a comprehensive and systematic review of available techniques and architectures, so that they can be easily followed by system and hardware designers to develop en/decoder implementations that meet error-correcting performance and cost requirements. This book can be also used as a reference for graduate-level courses on VLSI design and error-correcting coding. Particular emphases are placed on hard- and soft-decision Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes, and binary and non-binary low-density parity-check (LDPC) codes. These codes are among the best candidates for modern and emerging applications due to their good error-correcting performance and lower implementation complexity compared to other codes. To help explain the computations and en/decoder architectures, many examples and case studies are included.

More importantly, discussions are provided on the advantages and drawbacks of different implementation approaches and architectures.

錯誤修正碼是無所不在的。它們被應用在幾乎所有現代數位通訊和儲存系統中，例如無線通訊、光學通訊、快閃記憶體、電腦硬碟、感測器網路和深空探測等。新一代和新興應用需要具有更好錯誤修正能力的碼。然而，這些高增益錯誤修正碼的設計和實現面臨許多挑戰。它們通常涉及複雜的數學計算，直接映射到硬體上往往導致非常高的複雜度。

《現代錯誤修正碼的VLSI架構》作為連接編碼理論進展與實際硬體實現的橋樑。該書不僅關注電路級設計技術，還突出了整合的演算法和架構轉換，以在硬體實現中實現吞吐量、硅面積需求和/或功耗的巨大改進。

本書的目標是提供一個全面而系統的技術和架構評估，以便系統和硬體設計師能夠輕鬆地開發符合錯誤修正性能和成本要求的編/解碼器實現。本書也可作為研究生級別的VLSI設計和錯誤修正編碼課程的參考書。特別強調硬判斷和軟判斷的Reed-Solomon (RS)和Bose-Chaudhuri-Hocquenghem (BCH)碼，以及二進制和非二進制的低密度奇偶校驗 (LDPC) 碼。這些碼由於其良好的錯誤修正性能和較低的實現複雜度，是現代和新興應用的最佳選擇之一。為了幫助解釋計算和編/解碼器架構，書中包含了許多例子和案例研究。

更重要的是，書中討論了不同實現方法和架構的優點和缺點。