Logical Effort: Designing Fast CMOS Circuits
Ivan Sutherland, Robert F. Sproull, David Harris
 出版商: Morgan Kaufmann
 出版日期: 19990216
 定價: USD $81.95
 售價: $3,633
 貴賓價: 9.5 折 $3,451
 語言: 英文
 頁數: 256
 裝訂: Paperback
 ISBN: 1558605576
 ISBN13: 9781558605572
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Designers of highspeed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed targets. Logical Effort: Designing Fast CMOS Circuits makes high speed design easier and more methodical, providing a simple and broadly applicable method for estimating the delay resulting from factors such as topology, capacitance, and gate sizes.
The brainchild of circuit and computer graphics pioneers Ivan Sutherland and Bob Sproull, "logical effort" will change the way you approach design challenges. This book begins by equipping you with a sound understanding of the method's essential procedures and conceptsso you can start using it immediately. Later chapters explore the theory and finer points of the method and detail its specialized applications.
Features
 Explains the method and how to apply it in two practically focused chapters.
 Improves circuit design intuition by teaching simple ways to discern the consequences of topology and gate size decisions.
 Offers easy ways to choose the fastest circuit from among an array of potential circuit designs.
 Reduces the time spent on tweaking and simulationsso you can rapidly settle on a good design.
 Offers indepth coverage of specialized areas of application for logical effort: skewed or unbalanced gates, other circuit families (including pseudoNMOS and domino), wide structures such as decoders, and irregularly forking circuits.
 Presents a complete derivation of the methodso you see how and why it works.
Ivan E. Sutherland, a vice president and fellow at Sun Microsystems, received the Turing Award and the Von Neumann Medal for his pioneering contributions in the fields of computer graphics and microelectronic design.
Robert F. Sproull is an internationally noted expert on the design of graphics hardware and software. He too is a vice president and fellow at Sun.
David Harris is Assistant Professor of Engineering at Harvey Mudd College. He has made logical effort an integral part of his approach to teaching highspeed CMOS circuit design.
Table of Contents:
1 The Method of Logical Effort
2 Design Examples
3 Deriving the Method of Logical Effort
4 Calculating the Logical Effort of Gates
5 Calibrating the Model
6 Asymmetric Logic Gates
7 Unequal Rising and Falling Delays
8 Circuit Families
9 Forks of Amplifiers
10 Branches and Interconnect
11 Wide Structures
12 Conclusions
A Cast of Characters
B Reference process parameters
C Logical Effort Tools
D Solutions
 A detailed example of logical effort applied to the design of a multiplier.
 The Perl script used in Chapter 5 to characterize the logical effort of gates. The script takes a SPICE netlist of the gates, a process file, and a list of input stimuli for each gate. It measures the logical effort and parasitic delay of each gate using the test setup described in Chapter 5. (You must have an HSPICE license to use this program. The script comes with no warranty or technical support and is only intended as an example of the material discussed in Chapter 5.)
 A Java tool to design NAND, NOR, AND, and OR gates. It takes the number of inputs and the electrical effort of the path and computes the minimum delay tree, as discussed in Section 11.1. This tool can be used from a formbased interface on the Web, or downloaded for use on your computer.
 Chapter 1 in PDF format.
 Solutions to evennumbered exercises. [Available to instructors only; request a password from your academic sales representative]
 Electronic versions of text figures