Logical Effort: Designing Fast CMOS Circuits

Ivan Sutherland, Robert F. Sproull, David Harris

  • 出版商: Morgan Kaufmann
  • 出版日期: 1999-02-02
  • 售價: $2,840
  • 貴賓價: 9.5$2,698
  • 語言: 英文
  • 頁數: 256
  • 裝訂: Paperback
  • ISBN: 1558605576
  • ISBN-13: 9781558605572
  • 相關分類: CMOS
  • 海外代購書籍(需單獨結帳)

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Designers of high-speed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed targets. Logical Effort: Designing Fast CMOS Circuits makes high speed design easier and more methodical, providing a simple and broadly applicable method for estimating the delay resulting from factors such as topology, capacitance, and gate sizes.

The brainchild of circuit and computer graphics pioneers Ivan Sutherland and Bob Sproull, "logical effort" will change the way you approach design challenges. This book begins by equipping you with a sound understanding of the method's essential procedures and concepts-so you can start using it immediately. Later chapters explore the theory and finer points of the method and detail its specialized applications.

Features

  • Explains the method and how to apply it in two practically focused chapters.
  • Improves circuit design intuition by teaching simple ways to discern the consequences of topology and gate size decisions.
  • Offers easy ways to choose the fastest circuit from among an array of potential circuit designs.
  • Reduces the time spent on tweaking and simulations-so you can rapidly settle on a good design.
  • Offers in-depth coverage of specialized areas of application for logical effort: skewed or unbalanced gates, other circuit families (including pseudo-NMOS and domino), wide structures such as decoders, and irregularly forking circuits.
  • Presents a complete derivation of the method-so you see how and why it works.

Authors:

Ivan E. Sutherland, a vice president and fellow at Sun Microsystems, received the Turing Award and the Von Neumann Medal for his pioneering contributions in the fields of computer graphics and microelectronic design.

Robert F. Sproull is an internationally noted expert on the design of graphics hardware and software. He too is a vice president and fellow at Sun.

David Harris is Assistant Professor of Engineering at Harvey Mudd College. He has made logical effort an integral part of his approach to teaching high-speed CMOS circuit design.

Table of Contents:
1 The Method of Logical Effort
2 Design Examples
3 Deriving the Method of Logical Effort
4 Calculating the Logical Effort of Gates
5 Calibrating the Model
6 Asymmetric Logic Gates
7 Unequal Rising and Falling Delays
8 Circuit Families
9 Forks of Amplifiers
10 Branches and Interconnect
11 Wide Structures
12 Conclusions
A Cast of Characters
B Reference process parameters
C Logical Effort Tools
D Solutions

Web-Enhanced:

 

  • A detailed example of logical effort applied to the design of a multiplier.
  • The Perl script used in Chapter 5 to characterize the logical effort of gates. The script takes a SPICE netlist of the gates, a process file, and a list of input stimuli for each gate. It measures the logical effort and parasitic delay of each gate using the test setup described in Chapter 5. (You must have an HSPICE license to use this program. The script comes with no warranty or technical support and is only intended as an example of the material discussed in Chapter 5.)
  • A Java tool to design NAND, NOR, AND, and OR gates. It takes the number of inputs and the electrical effort of the path and computes the minimum delay tree, as discussed in Section 11.1. This tool can be used from a form-based interface on the Web, or downloaded for use on your computer.

Supplements

 

Errata:
For the first printing

Related Titles:

Computer Architecture & Design


 

商品描述(中文翻譯)


訂購本書 | 作者 | 目錄 | 網路增強 | 勘誤 | 相關書籍

 

高速集成電路的設計師面臨著眾多選擇,往往花費許多時間調整閘極以達到速度目標。《Logical Effort: Designing Fast CMOS Circuits》使高速設計更加容易和有系統,提供了一種簡單且廣泛適用的方法,用於估計拓撲、電容和閘極尺寸等因素導致的延遲。

這本書是電路和計算機圖形學先驅伊凡·薩瑟蘭和鮑勃·斯普勞爾的心血結晶,"logical effort"將改變您對設計挑戰的看法。本書首先讓您熟悉該方法的基本程序和概念,以便您可以立即開始使用。後面的章節探討了該方法的理論和細節,並詳細介紹了其專業應用。

特點


  • 在兩個實用的章節中解釋了該方法及如何應用。

  • 通過教授簡單的方法來判斷拓撲和閘極尺寸決策的後果,提高電路設計直覺。

  • 提供了從眾多潛在電路設計中選擇最快電路的簡便方法。

  • 減少了調整和模擬所花費的時間,使您能夠快速確定一個好的設計。

  • 深入介紹了logical effort的專業應用領域:不對稱或不平衡閘極、其他電路家族(包括偽NMOS和多米諾)、解碼器等寬結構,以及不規則分叉電路。

  • 完整推導了該方法,讓您了解它的工作原理和原因。

作者:

Ivan E. Sutherland,Sun Microsystems的副總裁和研究員,因在計算機圖形學和微電子設計領域的開創性貢獻而獲得圖靈獎和馮·諾伊曼獎。

Robert F. Sproull是國際知名的圖形硬件和軟件設計專家,也是Sun的副總裁和研究員。

David Harris是哈維穆德學院工程學助理教授。他將logical effort作為教授高速CMOS電路設計的方法的一部分。

目錄:

1 logical effort方法

2 設計示例

3 推導logical effort方法

4 計算閘極的logical effort

5 校準模型

6 不對稱邏輯閘

7 上升和下降延遲不相等

8 電路家族

9 放大器的分叉

10 分支和互連

11 寬結構

12 結論

A 人物角色

B 參考過程參數

C logical effort工具```