Designing with FPGAs and CPLDs

Bob Zeidman

  • 出版商: CMP Books
  • 出版日期: 2002-01-11
  • 售價: $2,100
  • 貴賓價: 9.5$1,995
  • 語言: 英文
  • 頁數: 240
  • 裝訂: Paperback
  • ISBN: 1578201128
  • ISBN-13: 9781578201129
  • 相關分類: FPGA

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商品描述

  • Choose the right programmable logic devices and development tools
  • Understand the design, verification, and testing issues
  • Plan schedules and allocate resources efficiently

Choose the right programmable logic devices with this guide to the technologies and internal architectures of Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). This complete reference is written in easy-to-understand language intended for engineers who are planning a CPLD-based or FPGA-based design; managers who need to plan, schedule, and budget a CPLD-based or FPGA-based design; and board-level designers who need to design CPLDs or FPGAs into a product. Experienced designers will find well-structured guidelines for future projects. The author explains the entire procedure for designing these devices from specification through production.

Programmable logic devices are explained in an overview, leading up to a detailed description of CPLDs and FPGAs. The various architectures are examined thoroughly along with the tradeoffs - allowing you to decide which particular device is right for your design. Engineers learn about important design, verification, synthesis, and testing issues for producing an optimized and reliable design as well as the different Electronic Design Automation (EDA) tools available. Engineering managers learn how to use the step-by-step Universal Design Methodology (UDM) to optimally allocate resources and to schedule and budget the development process accurately.

Table of Contents

Foreword

Preface

Acknowledgments

Chapter 1 Prehistory: Programmable Logic to ASICs

Chapter 2 Complex Programmable Logic Devices (CPLDs)

Chapter 3 Field Programmable Gate Arrays (FPGAs)

Chapter 4 Universal Design Methodology for Programmable Devices

Chapter 5 Design Techniques, Rules, and Guidelines

Chapter 6 Verification

Chapter 7 Electronic Design Automation Tools

Chapter 8 Today and The Future

Appendix A Answer Key

Appendix B Verilog Code for Schematics in Chapter 6

Glossary

References

About the Author

Index