Low power BIST for VLSI Digital Circuits
暫譯: 低功耗自測試技術於VLSI數位電路

In recent years, power consumption gained importance as one of the major concerns of VLSI designers. The primary driving factor for this trend has been the diffusion of battery powered portable computing devices and wireless communication systems. For this new class of battery powered devices average power consumption is critical, since it determines battery life. A strong pressure for reducing power dissipation is also coming from producers of high-end systems. In digital VLSI, the circuits using irreversible logic will have more amount of power dissipation due to unequal number of inputs and outputs. Due to these mismatching number of inputs and outputs an amount, KTln2 joules of energy loss occurs for each bit of information loss, where K is Boltzmann's constant (1.38 x 10-23 joules/Kelvin) and T is the absolute temperature in 0K. An alternative way to have low power in VLSI is making use of reversible logic. Reversible logic reduces power dissipation by having equal number of inputs and outputs without any loss of bit information. Therefore, in this work various digital circuits such as decoder, encoder, priority encoder, multiplexer, demultiplexer, ALU and multipliers.