Recent Advances in Pmos Negative Bias Temperature Instability: Characterization and Modeling of Device Architecture, Material and Process Impact
暫譯: PMOS 負偏壓溫度不穩定性的最新進展：裝置架構、材料與製程影響的特徵化與建模
Mahapatra, Souvik
相關主題
商品描述
This book covers advances in Negative Bias Temperature Instability (NBTI) and will prove useful to researchers and professionals in the semiconductor devices areas. NBTI continues to remain as an important reliability issue for CMOS transistors and circuits. Development of NBTI resilient technology relies on utilizing suitable stress conditions, artifact free measurements and accurate physics-based models for the reliable determination of degradation at end-of-life, as well as understanding the process, material and device architectural impacts. This book discusses:
- BTI Analysis Tool (BAT), a comprehensive physics-based framework, to model the measured time kinetics of parametric drift during and after DC and ACstress, at different stress and recovery biases and temperature, as well as pulse duty cycle and frequency.
- The Reaction Diffusion (RD) model is used for generated interface traps, Transient Trap Occupancy Model (TTOM) for charge occupancy of the generated interface traps and their contribution, Activated Barrier Double Well Thermionic (ABDWT) model for hole trapping in pre-existing bulk gate insulator traps, and Reaction Diffusion Drift (RDD) model for bulk trap generation in the BAT framework; NBTI parametric drift is due to uncorrelated contributions from the trap generation (interface, bulk) and trapping processes.
商品描述(中文翻譯)
這本書涵蓋了負偏壓溫度不穩定性（Negative Bias Temperature Instability, NBTI）的進展，對於半導體器件領域的研究人員和專業人士將非常有用。NBTI 仍然是 CMOS 晶體管和電路的一個重要可靠性問題。開發 NBTI 抗性技術依賴於利用適當的應力條件、無干擾的測量和準確的基於物理的模型，以可靠地確定終端壽命的退化，以及理解過程、材料和器件架構的影響。本書討論了：
- 由於 NBTI 在不同晶體管架構中引起的參數漂移的超快速測量和建模：平面大塊和 FDSOI p-MOSFET、p-FinFET 和 GAA-SNS p-FET，使用矽和矽鍺通道。
- BTI 分析工具（BTI Analysis Tool, BAT），這是一個全面的基於物理的框架，用於建模在不同應力和恢復偏壓及溫度下，DC 和 AC 應力期間及之後的參數漂移的測量時間動力學，以及脈衝佔空比和頻率。
- 反應擴散（Reaction Diffusion, RD）模型用於生成界面陷阱，瞬態陷阱佔用模型（Transient Trap Occupancy Model, TTOM）用於生成的界面陷阱的電荷佔用及其貢獻，激活障礙雙井熱電子（Activated Barrier Double Well Thermionic, ABDWT）模型用於在預先存在的大塊閘介質陷阱中進行孔捕獲，以及反應擴散漂移（Reaction Diffusion Drift, RDD）模型用於在 BAT 框架中生成大塊陷阱；NBTI 參數漂移是由於來自陷阱生成（界面、大塊）和捕獲過程的無關貢獻。
- 對氮掺入閘介質、鍺掺入通道以及由於晶體管佈局或器件尺寸變化引起的機械應力效應的分析和建模；分析了（100）表面主導的平面和 GAA MOSFET 與（110）側壁主導的 FinFET 的相似性和差異。
作者簡介
Souvik Mahapatra received his Bachelors and Masters degrees in Physics from Jadavpur University, Calcutta, India in 1993 and 1995 respectively, and PhD in Electrical Engineering from IIT Bombay, Mumbai, India in 1999. During 2000-2001, he was with Bell Laboratories, Lucent Technolgies, Murray Hill, NJ, USA. Since 2002 he is with IIT Bombay, and is currently the PK Kelkar Chair Professor in the Department of Electrical Engineering. His primary research interests are in the areas of semiconductor device characterization, modeling and simulation, and in particular, MOS transistor and Flash memory device scaling and reliability. He has interacted closely with major semiconductor industries in the world, and has contributed in several technologically relevant research topics such as MOS gate insulator scaling, Bias Temperature Instability and Hot Carrier Degradation in CMOS devices, CHISEL NOR Flash, SONOS NOR and NAND Flash memory devices. He has authored and co-authored more than 190 papers in peer reviewed journals and conferences and several book chapters, and delivered invited talks and tutorials in major international conferences around the world, including at the IEEE IEDM and IEEE IRPS. He has served as a distinguished lecturer of the IEEE EDS, chair of the IEEE EDS device reliability physics subcommittee, and in paper selection subcommittees and as session chairs in several IEEE conferences. He is a fellow of Institute of Electrical and Electronics Engineers (IEEE), Indian National Science Academy (INSA), Indian National Academy of Engineering (INAE) and Indian Academy of Sciences (IASc).
作者簡介(中文翻譯)
Souvik Mahapatra 於1993年和1995年分別在印度加爾各答的賈達布爾大學獲得物理學學士和碩士學位，並於1999年在印度孟買的印度理工學院（IIT Bombay）獲得電機工程博士學位。在2000年至2001年間，他曾在美國新澤西州的貝爾實驗室（Bell Laboratories）、盧森特科技（Lucent Technologies）工作。自2002年以來，他一直在印度理工學院（IIT Bombay）任教，目前擔任電機工程系的PK Kelkar講座教授。他的主要研究興趣包括半導體器件的特性、建模和模擬，特別是MOS晶體管和Flash記憶體器件的縮放和可靠性。他與全球主要的半導體產業有密切的互動，並在多個技術相關的研究主題上做出了貢獻，例如MOS閘極絕緣層的縮放、CMOS器件中的偏壓溫度不穩定性（Bias Temperature Instability）和熱載流子退化（Hot Carrier Degradation）、CHISEL NOR Flash、SONOS NOR和NAND Flash記憶體器件。他在同行評審的期刊和會議上發表和共同發表了超過190篇論文及數個書章，並在全球主要國際會議上發表受邀演講和教程，包括IEEE IEDM和IEEE IRPS。他曾擔任IEEE EDS的傑出講師、IEEE EDS器件可靠性物理子委員會的主席，以及多個IEEE會議的論文選擇子委員會和會議主席。他是電氣和電子工程師學會（IEEE）、印度國家科學院（INSA）、印度國家工程院（INAE）和印度科學院（IASc）的院士。
