Verilog HDL: A Guide to Digital Design and Synthesis, 2/e (Paperback)

Samir Palnitkar

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<內容簡介>

Appropriate for all courses in digital IC or system design using the Verilog Hardware Description Language (HDL). Fully updated for the latest versions of Verilog HDL, this complete reference progresses logically from the most fundamental Verilog concepts to today's most advanced digital design techniques. Written for both experienced students and newcomers, it offers broad coverage of Verilog HDL from a practical design perspective. One step at a time, Samir Palnitkar introduces students to gate, dataflow (RTL), behavioral, and switch level modeling; presents the Programming Language Interface (PLI); describes leading logic synthesis methodologies; explains timing and delay simulation; and introduces many other essential techniques for creating tomorrows complex digital designs. Palnitkar offers a wealth of proven Verilog HDL modeling tips, and more than 300 fully-updated illustrations, examples, and exercises. Each chapter contains detailed learning objectives and convenient summaries.

<章節目錄>
I. BASIC VERILOG TOPICS.

1. Overview of Digital Design with Verilog HDL.

2. Hierarchical Modeling Concepts.

3. Basic Concepts.

4. Modules and Ports.

5. Gate Level Modeling.

6. Data Flow Modeling.

7. Behavioral Modeling.

8. Tasks and Functions.

9. Useful Modeling Techniques.

II. ADVANCED VERILOG TOPICS.

10. Timing and Delays.

11. Switch Level Modeling.

12. User Defined Primitives

13. Programming Language Interface.

14. Logic Synthesis with Verilog HDL.

III. APPENDICES.

Appendix A. Strength Modeling and Advanced Net Definitions.

Appendix B. List of PLI Routines.

Appendix C. List of Keywords, System Tasks and Compiler

Directives.

Appendix D. Formal Syntax Definition.

Appendix E. Verilog Tidbits.

Appendix F. Verilog Examples.

Bibliography.