MLIR and the Modern Compiler: Building High-PerformanceDomain-Specific Languages for Hardware Accelerators.
暫譯: MLIR 與現代編譯器：為硬體加速器構建高效能領域特定語言

The era of monolithic intermediate representations is over. When building Domain-Specific Languages (DSLs) for modern AI hardware, GPUs, and custom Neural Processing Units (NPUs), relying solely on traditional LLVM IR creates an insurmountable phase-ordering dilemma. By the time your code reaches the optimizer, critical high-level structural semantics are completely lost, making advanced polyhedral loop transformations and hardware-specific memory mappings nearly impossible.

MLIR and the Modern Compiler: Building High-Performance Domain-Specific Languages for Hardware Accelerators is the definitive, bare-metal engineering manual for the Multi-Level Intermediate Representation (MLIR) framework. This book provides compiler engineers, hardware architects, and C++ systems developers with the exact blueprints required to construct zero-overhead compilation pipelines that lower high-level domain operations directly into hyper-optimized machine code and synthesizable hardware logic.

Inside, you will discover:

• Custom Dialect Architecture: Master the TableGen (ODS) infrastructure. Systematically declare custom operations, regions, traits, and interfaces to build fully modular, reusable intermediate representations.
• Progressive Lowering & Bufferization: Stop fighting memory allocations. Architect seamless conversion targets that lower high-level functional tensor abstractions down to structured MemRef operations with one-shot bufferization.
• Affine & Vector Optimizations: Weaponize the Affine dialect to execute multidimensional loop tiling and fusion. Drive structured polyhedral tracking to minimize cache thrashing and map vector operations natively onto hardware SIMD architectures.
• The Transform Dialect: Manipulate IR and orchestrate complex loop unrolling and thread mapping entirely through declarative optimization schedules-without writing a single custom C++ pass.
• GPU & NPU Emission: Execute complex GPU execution model mapping. Handle asynchronous memory transfers via token streams, and finalize MLIR modules into target-specific LLVM IR strings for bare-metal assembly.
• Hardware Synthesis Integration (CIRCT): Cross the software-hardware boundary. Lower structural dataflow semantics directly into synthesizable Verilog and SystemVerilog blocks while managing strict clock-cycle boundaries.

Engineered for the practitioner who needs to bootstrap an out-of-tree MLIR project immediately, the Reference chapters provide production-ready utility:

• Minimal Dialect Scaffold: The complete, modern boilerplate C++ templates required to initiate a custom out-of-tree MLIR project.
• Custom Trait Matrix: A quick-reference architecture guide for defining memory effects, structural invariants, and side-effect profiles.
• Pipeline Optimization Flags: The definitive reference for mlir-opt and mlir-translate command-line configurations used in production environments.