Electronic Design Automation: Synthesis, Verification, and Test (Hardcover)

Laung-Terng Wang, Kwang-Ting (Tim) Cheng, Yao-Wen Chang

  • 出版商: Morgan Kaufmann
  • 出版日期: 2009-03-12
  • 售價: $1,300
  • 貴賓價: 9.5$1,235
  • 語言: 英文
  • 頁數: 972
  • 裝訂: Hardcover
  • ISBN: 0123743648
  • ISBN-13: 9780123743640

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<本書特色>

1 .  Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test...helps EDA newcomers to get "up-and-running" quickly;
2 .  Comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures...helps all readers improve their VLSI design competence;
3 .  Latest advancements, not yet available in other books, including Test compression, ESL design modeling, Large-scale floorplanning, Placement, Routing, Synthesis of clock and power/ground networks...helps readers to design/develop testable chips or products;
4 .  Includes industry best-practices wherever appropriate in most chapters...helps readers avoid costly mistakes

<內容簡介>

This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book.

<章節目錄>

Introduction
Fundamentals of CMOS Design
Design for Testability
Fundamentals of Algorithms
Electronic System-Level Design and Modeling
High-Level Synthesis
Logic Synthesis
Test Synthesis
Logic and Circuit Simulation
Functional Verification
Floorplanning
Placement
Global and Detailed Routing
Synthesis of Clock and Power/Ground Networks
Fault Simulation and Test Generation.