Active-HDL 6.3 Student Edition
暫譯: Active-HDL 6.3 學生版

Description:

This entry-level Electronic Design Automation (EDA) software tool is based on the same award-winning EDA tool used by professional logic circuit designers every day.  Using the identical menus, icons and design flows that have become EDA industry standards, Active-HDL Student Edition 6.3 is a valuable educational resource for novices. KEY TOPICS: Allows experimentation with entry level "softcore" Intellectual Property (IP) design entry techniques Onboard sample designs and training exercises. Offers Design Entry features such as support for either Verilog or VHDL language designs (non-mixed), Verilog and VHDL libraries, Hardware Description Language Editor (HDE), and Block Diagram Editor (BDE). Provides Simulation and Debugging features such as VHDL/Verilog Testbench generation with easy to use "wizard" for creating input stimulus signals, Waveform Viewer, and Follow Objects feature for debugging. MARKET: A useful guide for electrical engineers who need to learn an EDA software tool.