Digital System Design with SystemVerilog (Hardcover)

Mark Zwolinski

  • 出版商: Prentice Hall
  • 出版日期: 2009-11-02
  • 售價: $4,060
  • 貴賓價: 9.5$3,857
  • 語言: 英文
  • 頁數: 408
  • 裝訂: Hardcover
  • ISBN: 0137045794
  • ISBN-13: 9780137045792
  • 相關分類: Verilog
  • 已絕版
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商品描述

The Definitive, Up-to-Date Guide to Digital Design with SystemVerilog: Concepts, Techniques, and Code

To design state-of-the-art digital hardware, engineers first specify functionality in a high-level Hardware Description Language (HDL)—and today’s most powerful, useful HDL is SystemVerilog, now an IEEE standard. Digital System Design with SystemVerilog is the first comprehensive introduction to both SystemVerilog and the contemporary digital hardware design techniques used with it.

Building on the proven approach of his bestselling Digital System Design with VHDL, Mark Zwolinski covers everything engineers need to know to automate the entire design process with SystemVerilog—from modeling through functional simulation, synthesis, timing simulation, and verification. Zwolinski teaches through about a hundred and fifty practical examples, each with carefully detailed syntax and enough in-depth information to enable rapid hardware design and verification. All examples are available for download from the book's companion Web site, zwolinski.org.

Coverage includes

 

  • Using electronic design automation tools with programmable logic and ASIC technologies
  • Essential principles of Boolean algebra and combinational logic design, with discussions of timing and hazards
  • Core modeling techniques: combinational building blocks, buffers, decoders, encoders, multiplexers, adders, and parity checkers
  • Sequential building blocks: latches, flip- flops, registers, counters, memory, and sequential multipliers
  • Designing finite state machines: from ASM chart to D flip-flops, next state, and output logic
  • Modeling interfaces and packages with SystemVerilog
  • Designing testbenches: architecture, constrained random test generation, and assertion-based verification
  • Describing RTL and FPGA synthesis models
  • Understanding and implementing Design-for-Test
  • Exploring anomalous behavior in asynchronous sequential circuits
  • Performing Verilog-AMS and mixed-signal modeling

Whatever your experience with digital design, older versions of Verilog, or VHDL, this book will help you discover SystemVerilog’s full power and use it to the fullest.
 

 

商品描述(中文翻譯)

《SystemVerilog數位設計的權威、最新指南:概念、技術和程式碼》

為了設計最先進的數位硬體,工程師首先使用高階硬體描述語言(HDL)來指定功能,而今天最強大、最有用的HDL是SystemVerilog,現在已成為IEEE標準。《SystemVerilog數位系統設計》是第一本全面介紹SystemVerilog和與之一起使用的當代數位硬體設計技術的書籍。

Mark Zwolinski在他暢銷書《使用VHDL進行數位系統設計》的基礎上,介紹了工程師需要了解的使用SystemVerilog自動化整個設計流程的所有知識,從建模到功能模擬、綜合、時序模擬和驗證。Zwolinski通過約150個實用示例進行教學,每個示例都有仔細詳細的語法和足夠深入的信息,以實現快速的硬體設計和驗證。所有示例都可以從書的附屬網站zwolinski.org上下載。

內容包括:

- 使用可程式邏輯和ASIC技術的電子設計自動化工具
- 布林代數和組合邏輯設計的基本原理,包括時序和危害的討論
- 核心建模技術:組合式構建塊、緩衝器、解碼器、編碼器、多路復用器、加法器和奇偶校驗器
- 順序式構建塊:鎖存器、觸發器、寄存器、計數器、記憶體和順序乘法器
- 設計有限狀態機:從ASM圖到D觸發器、下一狀態和輸出邏輯
- 使用SystemVerilog建模介面和封裝
- 設計測試平台:架構、受限隨機測試生成和基於斷言的驗證
- 描述RTL和FPGA綜合模型
- 理解和實現測試設計
- 探索異步順序電路中的異常行為
- 執行Verilog-AMS和混合信號建模

無論您對數位設計、舊版Verilog還是VHDL有何經驗,本書都將幫助您發現SystemVerilog的全部威力並充分利用它。