VHDL for Engineers (IE)
暫譯: 工程師的VHDL

<內容簡介>

Suitable for use in a one- or two-semester course for computer and electrical engineering majors.VHDL for Engineers teaches readers how to design and simulate digital systems using the hardware description language, VHDL. These systems are designed for implementation using programmable logic devices (PLDs) such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). The book focuses on writing VHDL design descriptions and VHDL testbenches. The steps in VHDL/PLD design methodology are also a key focus. Short presents the complex VHDL language in a logical manner, introducing concepts in an order that allows the readers to begin producing synthesizable designs as soon as possible.

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Preface

1 Di g i t a l Design Using VHDL and PLDs 1

2 E n t it i e s , Archi t e ct u r e s , and Cod ing S t y les 44

3 Signals and Data Types 82

4 Dataf low Style Combinational Design 123

5 Behavi o r a l S t y le Combinational Design 165

6 Event-Dr i v en Simulation 201

7 Testbenche s for Combinational Designs 251

8 Latches and F l i p - f l ops 304

9 Multibi t L a t ches, Regist e r s , Count e r s ,

and Memory 337

10 F i n i te State Machines 380

11 ASM Charts and RTL Des i gn 431

12 Subprograms 469

13 Packages 501

14 Testbenches for S equent i a l S y s tems 526

15 Modular Des ign and Hie rarchy 566

16 More Des ign Examples 615

Appendix VHDL At t r i b u t e s 659

Bibliography 663

Index