Monolithic Phase-locked Loops And Clock Recovery Circuits: Theory And Design (a Selected Reprint Volume)

Razavi

  • 出版商: Wiley
  • 出版日期: 1996-04-18
  • 售價: $8,300
  • 貴賓價: 9.5$7,885
  • 語言: 英文
  • 頁數: 508
  • 裝訂: Hardcover
  • ISBN: 0780311493
  • ISBN-13: 9780780311497
  • 相關分類: CMOS電子學 Eletronics電路學 Electric-circuits
  • 海外代購書籍(需單獨結帳)
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商品描述

Description:

Featuring an extensive 40 page tutorial introduction, this carefully compiled anthology of 65 of the most important papers on phase-locked loops and clock recovery circuits brings you comprehensive coverage of the field-all in one self-contained volume. You'll gain an understanding of the analysis, design, simulation, and implementation of phase-locked loops and clock recovery circuits in CMOS and bipolar technologies along with valuable insights into the issues and trade-offs associated with phase locked systems for high speed, low power, and low noise.

 

Table of Contents:

Preface.

Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits—A Tutorial (B. Razavi).

BASIC THEORY.

Theory of AFC Synchronization (W. Gruen).

Color-Carrier Reference Phase Synchronization Accuracy in NTSC Color Television (D. Richman).

Charge-Pump Phase-Locked Loops (F. Gardner).

z-Domain Model for Discrete-Time PLLs (J. Hein & J. Scott).

Analyze PLLs with Discrete Time Modeling (J. Kovacs).

Properties of Frequency Difference Detectors (F. Gardner).

Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery (D. Messerschmitt).

Analysis of Phase-Locked Timing Extraction Circuits for Pulse Code Transmission (E. Roza).

Optimization of Phase-Locked Loop Performance in Data Recovery Systems (R. Co & J. Mulligan).

Noise Properties of PLL Systems (V. Kroupa).

PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design (B. Kim, et al.).

Practical Approach Augurs PLL Noise in RF Synthesizers (M. O'Leary).

The Effects of Noise in Oscillators (E. Hafner).

A Simple Model of Feedback Oscillator Noise Spectrum (D. Leeson).

Noise in Relaxation Oscillators (A. Abidi & R. Meyer).

Analysis of Timing Jitter in CMOS Ring Oscillators (T. Weigandt, et al.).

Analysis, Modeling, and Simulation of Phase Noise in Monolithic Voltage-Controlled Oscillators (B. Razavi).

BUILDING BLOCKS.

Start-up and Frequency Stability in High-Frequency Oscillators (N. Nguyen & R. Meyer).

MOS Oscillators with Multi-Decade Tuning Range and Gigahertz Maximum Speed (M. Banu).

A Bipolar 1 GHz Multi-Decade Monolithic Variable-Frequency Oscillator (J. Wu).

A Digital Phase and Frequency Sensitive Detector (J. Brown).

A 3-State Phase Detector Can Improve Your Next PLL Design (C. Sharpe).

GaAs Monolithic Phase/Frequency Discriminator (I. Shahriary, et al.).

A New Phase-Locked Loop Timing Recovery Method for Digital Regenerators (J. Bellisio).

A Phase-Locked Loop with Digital Frequency Comparator for Timing Signal Recovery (J. Afonso, et al.).

Clock Recovery from Random Binary Signals (J. Alexander).

A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s (A. Pottbacker, et al.).

A Self-Correcting Clock Recovery Circuit (C. Hogge).

MODELING AND SIMULATION.

An Integrated PLL Clock Generator for 275 MHz Graphic Displays (G. Gutierrez & D. DeSimone).

The Macro Modeling of Phase-Locked Loopes for the SPICE Simulator (M. Sitkowski).

Modeling and Simulation of an Analog Charge Pump Phase-Locked Loop (S. Can & Y. Sahinkaya).

Mixed-Mode Simulation of Phase-Locked Loops (B. Antao, et al.).

Behavioral Representation for VCO and Detectors in Phase-Lock Systems (E. Liu & A. Sangiovanni-Vincentelli).

Behavioral Simulation Techniques for Phase/Delay-Locked Systems (A. Demir, et al.).

PHASE-LOCKED LOOPS.

A Monolithic Phase-Locked Loop with Detection Processor (E. Murthi).

A 200-MHz CMOS Phase-Locked Loop with Dual Phase Detectors (K. Ware, et al.).

High-Frequency Phase-Locked Loops in Monolithic Bipolar Technology (M. Soyuer & R. Meyer).

A 6-GHz Integrated Phase-Locked Loop Using AlGaAs/GaAs Heterojunction Bipolar Transistors (A. Buchwald, et al.).

A 6-GHz 60-mW BiCMOS Phase-Locked Loop with 2-V Supply (B. Razavi & J. Sung).

Design of PLL-Based Clock Generation Circuits (D. Jeong).

A Variable Delay Line PLL for CPU-Coprocessor Synchronization (M. Johnson & E. Hudson).

A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors (I. Young, et al.).

A Wide-Bandwidth Low-Voltage PLL for PowerPC Microprocessors (J. Alvarez, et al.).

A 30-128 MHz Frequency Synthesizer Standard Cell (R. Bitting & W. Repasky).

Cell-Based Fully Integrated CMOS Frequency Synthesizers (D. Mijuskovic, et al.).

Fully-Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and ±50 psec Jitter (I. Novof, et al.).

PLL Design for a 500 MB/s Interface (M. Horowitz, et al.).

CLOCK AND DATA RECOVERY CIRCUITS.

An Analog PLL-Based Clock and Data Recovery Circuit with High Input Jitter Tolerance (S. Sun).

A 30-MHz Hybrid Analog/Digital Clock Recovery Circuit in 2-μm CMOS (B. Kim, et al.).

A BiCMOS PLL-Based Data Separator Circuit with High Stability and Accuracy (S. Miyazawa, et al.).

A Versatile Clock Recovery Architecture and Monlithic Implementation (L. De Vito).

A 155-MHz Clock Recovery Delay- and Phase-Locked Loop (T. Lee & J. Bulzacchelli).

A Monolithic 156 Mb/s Clock and Data Recovery PLL Circuit using the Sample- and-Hold Technique (N. Ishihara & Y. Akazawa).

A Monolithic 480 Mb/s Parallel AGC/Decision/Clock Recovery Circuit in 1.2-μm CMOS (T. Hu & P. Gray).

A Monolithic 622 Mb/sec Clock Extraction and Data Retiming Circuit (B. Lai & R. Walker).

A 660 Mb/s CMOS Clock Recovery Circuit with Instantaneous Locking for NRZ Data and Burst-Mode Transmission (M. Banu & A. Dunlop).

A Monolithic 2.3-Gb/s 100-mW Clock and Data Recovery Circuit in Silicon Bipolar Technology (M. Soyuer).

A 50 MHz Phase- and Frequency-Locked Loop (R. Cordell, et al.).

NMOS ICs for Clock and Data Regeneration in Gigabit-per-Second Optical-Fiber Receivers (S. Enam & A. Abidi).

A PLL-Based 2.5-Gb/s Clock and Data Regenerator IC (H. Ransijn & P. O'Connor).

A 2.5-Gb/sec 15-mW BiCMOS Clock Recovery Circuit (B. Razavi & J. Sung).

An 8 GHz Silicon Bipolar Clock Recovery and Data Regenerator IC (A. Pottbacker & U. Langmann).

Author Index.

Subject Index.

Editor's Biography.

商品描述(中文翻譯)

描述:
這本精心編輯的文集收錄了65篇關於鎖相環和時鐘恢復電路的重要論文,並附有40頁的詳細教程介紹。這本書涵蓋了鎖相環和時鐘恢復電路在CMOS和雙極技術中的分析、設計、模擬和實現,並提供了有關高速、低功耗和低噪音鎖相系統相關問題和權衡的寶貴見解。

目錄:
前言。
單片鎖相環和時鐘恢復電路設計-教程(B. Razavi)。
基本理論。
AFC同步理論(W. Gruen)。
NTSC彩色電視中的色載波參考相位同步精度(D. Richman)。
電荷泵鎖相環(F. Gardner)。
離散時間PLL的z域模型(J. Hein和J. Scott)。
使用離散時間建模分析PLL(J. Kovacs)。
頻率差異檢測器的特性(F. Gardner)。
用於時序和載波恢復的PLL擷取頻率檢測器(D. Messerschmitt)。
用於脈衝編碼傳輸的鎖相定時提取電路分析(E. Roza)。
數據恢復系統中鎖相環性能優化(R. Co和J. Mulligan)。
PLL系統的噪聲特性(V. Kroupa)。
用於低抖動時鐘合成器設計的PLL / DLL系統噪聲分析(B. Kim等)。
實用方法預測射頻合成器中的PLL噪聲(M. O'Leary)。
振盪器中噪聲的影響(E. Hafner)。
反饋振盪器噪聲頻譜的簡單模型(D. Leeson)。
鬆弛振盪器中的噪聲(A. Abidi和R. Meyer)。
CMOS環形振盪器中的定時抖動分析(T. Weigandt等)。
單片壓控振盪器中相位噪聲的分析、建模和模擬(B. Razavi)。
基本組件。
高頻振盪器的啟動和頻率穩定性(N. Nguyen和R. Meyer)。
具有多十年調諧範圍和GHz最大速度的MOS振盪器(M. Banu)。
一個1 GHz多十年單片可變頻率振盪器(J. Wu)。
數字相位和頻率敏感檢測器(J. Brown)。
一個3狀態相位檢測器可以改善您的下一個PLL設計(C. Sharpe)。
GaAs單片相位/頻率鑑別器(I. Shahriary等)。
數字再生器的一種新的鎖相環定時恢復方法(J. Bellisio)。
具有數字頻率比較器的鎖相環用於定時信號恢復(J. Afonso等)。
從隨機二進制信號中恢復時鐘(J. Alexander)。
用於時鐘提取高達8 Gb/s的Si雙極相位和頻率檢測器IC(A. Pottbacker等)。
一個自校正時鐘恢復電路(C. Hogge)。
建模和模擬。
用於275 MHz圖形顯示器的集成PLL時鐘發生器(G. Gutierrez和D. DeSimone)。
SPICE模擬器中鎖相環的宏模型(M. Sitkowski)。
類比電荷泵鎖相環的建模和模擬(S. Can和Y. Sahinkaya)。
鎖相環的混合模擬(B. Antao等)。
相鎖系統中VCO和檢測器的行為表示(E. Liu和A. Sangiovanni-Vincentelli)。