Effective Coding with VHDL: Principles and Best Practice (Hardcover)

This book addresses an often-neglected aspect of the creation of VHDL designs. A VHDL description is also source code, and VHDL designers can use the best practices of software development to write high-quality code and to organize it in a design. This book presents this unique set of skills, teaching VHDL designers of all experience levels how to apply the best design principles and coding practices from the software world to the world of hardware. The concepts introduced here will help readers write code that is easier to understand and more likely to be correct, with improved readability, maintainability, and overall quality.

After a brief review of VHDL, the book presents fundamental design principles for writing code, discussing such topics as design, quality, architecture, modularity, abstraction, and hierarchy. Building on these concepts, the book then introduces and provides recommendations for each basic element of VHDL code, including statements, design units, types, data objects, and subprograms. The book covers naming data objects and functions, commenting the source code, and visually presenting the code on the screen. All recommendations are supported by detailed rationales. Finally, the book explores two uses of VHDL: synthesis and testbenches. It examines the key characteristics of code intended for synthesis (distinguishing it from code meant for simulation) and then demonstrates the design and implementation of testbenches with a series of examples that verify different kinds of models, including combinational, sequential, and FSM code. Examples from the book are also available on a companion website, enabling the reader to experiment with the complete source code.

本書探討了VHDL設計創作中常被忽視的一個方面。VHDL描述也是源代碼，VHDL設計師可以借鑒軟件開發的最佳實踐來編寫高質量的代碼並將其組織成一個設計。本書介紹了這一獨特的技能組合，教導各個經驗水平的VHDL設計師如何將軟件世界的最佳設計原則和編碼實踐應用到硬件世界中。本書介紹的概念將幫助讀者編寫更易於理解且更有可能正確的代碼，提高代碼的可讀性、可維護性和整體質量。

在對VHDL進行簡要回顧之後，本書提出了編寫代碼的基本設計原則，討論了設計、質量、架構、模塊化、抽象和層次結構等主題。在這些概念的基礎上，本書介紹並提供了對VHDL代碼的每個基本元素的建議，包括語句、設計單元、類型、數據對象和子程序。本書還涵蓋了命名數據對象和函數、對源代碼進行注釋以及在屏幕上視覺呈現代碼的方法。所有建議都有詳細的理由支持。最後，本書探討了VHDL的兩種用途：綜合和測試環境。它檢視了為綜合而設計的代碼的關鍵特點（區別於用於仿真的代碼），然後通過一系列示例演示了測試環境的設計和實現，驗證了不同類型模型的正確性，包括組合、時序和FSM代碼。本書的示例代碼也可在附帶網站上找到，讀者可以通過該網站實驗完整的源代碼。