Nano-CMOS Design for Manufacturability: Robust Circuit and Physical Design for Sub-65nm Technology Nodes (Hardcover)

Discover innovative tools that pave the way from circuit and physical design to fabrication processing

Nano-CMOS Design for Manufacturability examines the challenges that design engineers face in the nano-scaled era, such as exacerbated effects and the proven design for manufacturability (DFM) methodology in the midst of increasing variability and design process interactions. In addition to discussing the difficulties brought on by the continued dimensional scaling in conformance with Moore's law, the authors also tackle complex issues in the design process to overcome the difficulties, including the use of a functional first silicon to support a predictable product ramp. Moreover, they introduce several emerging concepts, including stress proximity effects, contour-based extraction, and design process interactions.

This book is the sequel to Nano-CMOS Circuit and Physical Design, taking design to technology nodes beyond 65nm geometries. It is divided into three parts:

• Part One, Newly Exacerbated Effects, introduces the newly exacerbated effects that require designers' attention, beginning with a discussion of the lithography aspects of DFM, followed by the impact of layout on transistor performance

• Part Two, Design Solutions, examines how to mitigate the impact of process effects, discussing the methodology needed to make sub-wavelength patterning technology work in manufacturing, as well as design solutions to deal with signal, power integrity, WELL, stress proximity effects, and process variability

• Part Three, The Road to DFM, describes new tools needed to support DFM efforts, including an auto-correction tool capable of fixing the layout of cells with multiple optimization goals, followed by a look ahead into the future of DFM

Throughout the book, real-world examples simplify complex concepts, helping readers see how they can successfully handle projects on Nano-CMOS nodes. It provides a bridge that allows engineers to go from physical and circuit design to fabrication processing and, in short, make designs that are not only functional, but that also meet power and performance goals within the design schedule.

發現從電路和物理設計到製造加工的創新工具

《Nano-CMOS Design for Manufacturability》探討了設計工程師在納米尺度時代面臨的挑戰，例如加劇的效應和在不斷增加的變異性和設計流程交互作用中被證明的可製造性設計（DFM）方法論。除了討論隨著摩爾定律持續尺寸縮小帶來的困難外，作者還解決了設計流程中的複雜問題，以克服這些困難，包括使用功能性的第一塊矽來支持可預測的產品上市。此外，他們還介紹了幾個新興概念，包括應力鄰近效應、基於輪廓的提取和設計流程交互作用。

這本書是《Nano-CMOS Circuit and Physical Design》的續集，將設計延伸到65nm以上的技術節點。它分為三個部分：

第一部分《新加劇的效應》介紹了需要設計師關注的新加劇的效應，從討論DFM的光刻方面開始，接著討論版圖對晶體管性能的影響。

第二部分《設計解決方案》探討如何減輕製程效應的影響，討論在製造中使次波長圖案技術發揮作用所需的方法論，以及處理信號、功率完整性、WELL、應力鄰近效應和製程變異性的設計解決方案。

第三部分《通往DFM的道路》描述了支持DFM工作所需的新工具，包括一個能夠修復具有多個優化目標的單元版圖的自動修正工具，並展望DFM的未來。

在整本書中，實際案例簡化了複雜的概念，幫助讀者了解如何成功處理Nano-CMOS節點上的項目。它提供了一個橋樑，讓工程師能夠從物理和電路設計轉向製造加工，簡而言之，製作出不僅功能正常，而且在設計進度內達到功率和性能目標的設計。