Designing Digital Computer Systems with Verilog

This unique book serves both as an introduction to computer architecture and as a guide to using a hardware description language (HDL) to design, model and simulate real digital systems. The book starts with an introduction to Verilog - the HDL chosen for the book since it is widely used in industry and straightforward to learn. Next, the instruction set architecture (ISA) for the simple VeSPA (Very Small Processor Architecture) processor is defined this is a real working device that has been built and tested at the University of Minnesota by the authors. The VeSPA ISA is used throughout the remainder of the book to demonstrate how behavioral and structural models can be developed and intermingled in Verilog. Although Verilog is used throughout, the lessons learned will be equally applicable to other HDLs. Written for senior and graduate students, this book is also an ideal introduction to Verilog for practising engineers.

• Unique approach combines tools and methods of VLSI design
• Uses industry standard Verilog hardware description software
• Complete ground-up approach covers all aspects of a real microprocessor design

 

Table of Contents

1. Controlling complexity; 2. A Verilogical place to start; 3. Defining the instruction set architecture; 4. Algorithmic behavioral modeling; 5. Building an assembler for VeSPA; 6. Pipelining; 7. Implementation of the pipelined processor; 8. Verification; A. The VeSPA instruction set architecture (ISA); B. The VASM assembler.

這本獨特的書既是一本介紹計算機架構的入門書，也是一本使用硬體描述語言（HDL）設計、建模和模擬真實數字系統的指南。本書以Verilog作為HDL的選擇，因為它在工業界被廣泛使用且易於學習。接下來，本書定義了簡單的VeSPA（Very Small Processor Architecture）處理器的指令集架構（ISA），這是一個在明尼蘇達大學由作者建造和測試的真實工作設備。在本書的其餘部分中，使用VeSPA ISA來展示如何在Verilog中開發和混合行為模型和結構模型。儘管全書都使用Verilog，但所學到的教訓同樣適用於其他HDL。本書針對高年級和研究生學生，也是實踐工程師學習Verilog的理想入門書。

目錄：
1. 控制複雜性
2. Verilog的起點
3. 定義指令集架構
4. 算法行為建模
5. 為VeSPA構建組譯器
6. 流水線處理
7. 流水線處理器的實現
8. 驗證
A. VeSPA指令集架構（ISA）
B. VASM組譯器