Verilog HDL: Digital Design and Modeling (Hardcover)

Joseph Cavanagh

  • 出版商: CRC
  • 出版日期: 2007-02-20
  • 售價: $1,350
  • 貴賓價: 9.8$1,323
  • 語言: 英文
  • 頁數: 920
  • 裝訂: Hardcover
  • ISBN: 1420051547
  • ISBN-13: 9781420051544
  • 相關分類: Verilog
  • 立即出貨 (庫存=1)

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商品描述

Description

  • Outlines the complete design of a reduced instruction set computer (RISC) processor using Verilog
  • Provides a detailed outline of the theory and design of a carry lookahead adder
  • Discusses both the Moore synchronous and asynchronous sequential machines as well as the Mealy pulse-mode asynchronous sequential machines
  • Covers the theory and design of a binary-coded decimal (BCD) adder/subtractor and a Booth algorithm-based multiplier
  • Includes downloadable slides containing Verilog code used in each chapter of the book

    Emphasizing the detailed design of various Verilog projects, Verilog HDL: Digital Design and Modeling offers students a firm foundation on the subject matter. The textbook presents the complete Verilog language by describing different modeling constructs supported by Verilog and by providing numerous design examples and problems in each chapter. Examples include counters of different moduli, half adders, full adders, a carry lookahead adder, array multipliers, different types of Moore and Mealy machines, and much more. The text also contains information on synchronous and asynchronous sequential machines, including pulse-mode asynchronous sequential machines.

    In addition, it provides descriptions of the design module, the test bench module, the outputs obtained from the simulator, and the waveforms obtained from the simulator illustrating the complete functional operation of the design. Where applicable, a detailed review of the topic's theory is presented together with logic design principles, including state diagrams, Karnaugh maps, equations, and the logic diagram.

    Verilog HDL: Digital Design and Modeling is a comprehensive, self-contained, and inclusive textbook that carries all designs through to completion, preparing students to thoroughly understand this popular hardware description language.

商品描述(中文翻譯)

描述

- 使用Verilog概述了一個精簡指令集(RISC)處理器的完整設計
- 提供了進位預測加法器的理論和設計的詳細概述
- 討論了Moore同步和非同步順序機以及Mealy脈衝模式非同步順序機
- 包括二進制編碼十進制(BCD)加減器/減法器和基於Booth算法的乘法器的理論和設計
- 包含可下載的幻燈片,其中包含書中每章使用的Verilog代碼

強調各種Verilog項目的詳細設計,《Verilog HDL: 數字設計和建模》為學生提供了堅實的基礎。該教科書通過描述Verilog支持的不同建模結構,並在每章提供大量的設計示例和問題,來介紹完整的Verilog語言。示例包括不同模數的計數器、半加器、全加器、進位預測加法器、數組乘法器、不同類型的Moore和Mealy機器等等。該教材還包含有關同步和非同步順序機的信息,包括脈衝模式非同步順序機。

此外,它還提供了設計模塊、測試台模塊、模擬器獲得的輸出以及模擬器獲得的波形,以展示設計的完整功能操作。在適用的情況下,還會詳細介紹該主題的理論,包括狀態圖、卡諾圖、方程式和邏輯圖等邏輯設計原則。

《Verilog HDL: 數字設計和建模》是一本全面、自包含且包容性的教科書,將所有設計都進行了完整的介紹,使學生能夠徹底理解這種流行的硬件描述語言。