Advanced ASIC Chip Synthesis: Using Synopsys Design Compiler Physical Compiler and PrimeTime, 2/e (Hardcover)

Himanshu Bhatnagar

  • 出版商: Springer
  • 出版日期: 2001-12-31
  • 售價: $9,640
  • 貴賓價: 9.5$9,158
  • 語言: 英文
  • 頁數: 328
  • 裝訂: Hardcover
  • ISBN: 0792376447
  • ISBN-13: 9780792376446
  • 相關分類: Compiler
  • 海外代購書籍(需單獨結帳)

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商品描述

Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime®, Second Edition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail.
The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basis of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution.
Target audiences for this book are practicing ASIC design engineers and masters level students undertaking advanced VLSI courses on ASIC chip design and DFT techniques.

商品描述(中文翻譯)

《Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime®, Second Edition》描述了在ASIC芯片合成、物理合成、形式验证和静态时序分析方面使用Synopsys工具套件的高级概念和技术。此外,本书还详细介绍了针对VDSM(超深亚微米)技术的整个ASIC设计流程方法论。

本书的重点是实时应用Synopsys工具来解决在VDSM几何结构中遇到的各种问题。读者将了解到一种处理复杂的亚微米ASIC设计的有效设计方法。重点放在HDL编码风格、合成和优化、动态仿真、形式验证、DFT扫插入、与布局的链接、物理合成和静态时序分析上。在每个步骤中,都会识别与设计流程的每个阶段相关的问题,并详细描述解决方案和解决方法。此外,还详细讨论了与布局相关的关键问题,包括时钟树合成和后端集成(与布局的链接)。

此外,本书还深入讨论了Synopsys技术库和HDL编码风格的基础,针对最佳合成解决方案。

本书的目标读者是从事ASIC设计工程师和攻读高级VLSI课程(关于ASIC芯片设计和DFT技术)的硕士级学生。