Advanced HDL Synthesis and SOC Prototyping: RTL Design Using Verilog (Hardcover)

Vaibbhav Taraate



This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies. The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike.


本書描述了使用Verilog進行RTL設計、系統單晶片(SOC)設計模塊的綜合和時序閉合。它涵蓋了SOC設計中複雜的RTL設計情景和挑戰,並提供了關於SOC和特定應用集成電路(ASIC)設計中性能改進的實用信息。本書還討論了使用現代高密度可編程閘陣列(FPGA)進行原型開發的實例和案例研究。本書討論了SOC設計、性能改進技術、測試和系統級驗證,同時描述了現代Intel FPGA/XILINX FPGA架構及其在SOC原型開發中的應用。此外,本書還介紹了Synopsys Design Compiler(DC)和Prime Time(PT)命令,以及如何使用它們來優化複雜的ASIC/SOC設計。本書的內容將對學生和專業人士都有用。