Verilog HDL Synthesis, A Practical Primer
J Bhasker
- 出版商: Star Galaxy Publishi
- 出版日期: 2018-05-21
- 售價: $2,670
- 貴賓價: 9.5 折 $2,537
- 語言: 英文
- 頁數: 236
- 裝訂: Paperback
- ISBN: 098462922X
- ISBN-13: 9780984629220
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相關分類:
Verilog
海外代購書籍(需單獨結帳)
商品描述
With this book, you can: - Start writing synthesizable Verilog models quickly. - See what constructs are supported for synthesis and how these map to hardware so that you can get the desired logic. - Learn techniques to help avoid having functional mismatches. - Immediately start using many of the models for commonly used hardware elements described for your own use or modify these for your own application.