Real World FPGA Design with Verilog

Ken Coffman

  • 出版商: Prentice Hall
  • 出版日期: 1999-12-08
  • 售價: $1,197
  • 語言: 英文
  • 頁數: 291
  • 裝訂: Paperback
  • ISBN: 0130998516
  • ISBN-13: 9780130998514
  • 相關分類: FPGAVerilog
  • 已絕版
    無現貨庫存(No stock available)





Real World Verilogguides you through every key challenge associated with designing FPGAs and ASICs using Verilog, one of the world's leading hardware design languages.KEY TOPICS:Start by walking a typical Verilog design all the way to silicon. Next, review basic Verilog syntax; design partitioning and synthesis issues; simulation and testing; combinatorial and sequential designs; black boxes and advanced simulation. You'll find irreverent yet rigorous coverage of what it really takes to translate HDL code into hardware -- and how to avoid the pitfalls that can occur along the way. Ken Coffman's no-frills, real-world design techniques can improve the stability and reliability of virtually any design. The accompanying CD-ROM includes working demo and student versions of popular Verilog, FPGA, synthesis, and simulation tools.MARKET:For anyone involved in Verilog design, especially entry-to-mid-level digital hardware designers.


Table of Contents:

1. Verilog Design in the Real World.

Trivial Overheat Detector Example. Synthesizable Verilog Elements. Verilog Hierarchy. Built-In Logic Primitives. Latches and Flipflops. Blocking and Nonblocking Assignments. Miscellaneous Verilog Syntax Items.

2. Digital Design Strategies and Techniques.

Design Processing Steps. Analog Building Blocks for Digital Primitives. Using a LUT to Implement Logic Functions. Discussion of Design Processing Steps. Synchronous Logic Rules. Clocking Strategies. Logic Minimization. What Does the Synthesizer Do? Area/Delay Optimization.

3. A Digital Circuit Toolbox.

Verilog Hierarchy Revisited. Tristate Signals and Busses. Bidirectional Busses. Priority Encoders. Area/Speed Optimization in Synthesis. Trade-off Between Operating Speed and Latency. Delays in FPGA Logic Elements. State Machines. Adders. Subtractors. Multipliers.

4. More Digital Circuits: Counters, RAMs, and FIFOs.

Ripple Counters. Johnson Counters. Linear Feedback Shift Registers. Cyclic Redundancy Checksums. ROM. RAM. FIFO Notes.

5. Verilog Test Fixtures.

Compiler Directives. Automated Testing.

6. Real World Design: Tools, Techniques, and Trade-offs.

Compiling with LeonardoSpectrum. Complete Design Flow, 8-Bit Equality Comparator. 8-Bit Equality Comparator with Hierarchy. Optimization Options In the Xilinx Environment. Mapping Options. Logic Level Timing Report/Post Layout Timing Report. VHDL/Verilog Simulation Options. Other Design Manager Tools.

7. A Look at Competing Architectures.

Factors that Determine Integrated Circuit Pricing. FPGA Device Design. FPGA Technology Selection Checklist. Xilinx FPGA Architectures. Altera CPLD Architectures.

8. Libraries, Reusable Modules, and IP.

Keys to Increased Productivity. Library Elements. Structural Coding Style. A Small Diversion to Compare a Schematic to a Verilog Design. Using LogiBLOX Module Generator. Design Reuse, Reusing Your Own Code. Buying IP Designs. Summing Up.

9. Designing for ASIC Conversion.

HardWire Devices. Semicustom Devices. Design Rules for ASIC Conversion. Synchronous Design Rules. Oscillators. Delay Lines. The Language of Test. Print-on-Change Test Vectors. Afterword-A Look into the Future. Resources. Glossary and Acronyms. Bibliography.


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