A SystemVerilog Primer
Bhasker, J.
- 出版商: Star Galaxy Publishing
- 出版日期: 2018-05-23
- 售價: $3,400
- 貴賓價: 9.5 折 $3,230
- 語言: 英文
- 頁數: 350
- 裝訂: Quality Paper - also called trade paper
- ISBN: 0984629238
- ISBN-13: 9780984629237
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相關分類:
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商品描述
This book is an excellent resource to get up to speed on the application of the various features of SystemVerilog per IEEE 1800-2009. The explanations of each feature is provided with examples and guidelines, where appropriate. This book is well organized and full of concrete examples that illustrates well on how to use SystemVerilog. It is a must primer for anyone who is beginning to learn SystemVerilog.
作者簡介
J. Bhasker is an Architect at eSilicon Corporation. Prior to that, he was a Distinguished Member of Technical Staff at Bell Laboratories. He has received a Meritorius Service Award from IEEE Computer Society for his technical contributions and continued leadership in the development of the EDA standards, especially the VHDL and Verilog RTL synthesis standards.
