SVA: The Power of Assertions in SystemVerilog

This book is a comprehensive guide to assertion-based verification of hardware designs using System Verilog Assertions (SVA). It enables readers to minimize the cost of verification by using assertion-based techniques in simulation testing, coverage collection and formal analysis. The book provides detailed descriptions of all the language features of SVA, accompanied by step-by-step examples of how to employ them to construct powerful and reusable sets of properties. The book also shows how SVA fits into the broader System Verilog language, demonstrating the ways that assertions can interact with other System Verilog components. The reader new to hardware verification will benefit from general material describing the nature of design models and behaviors, how they are exercised, and the different roles that assertions play. This second edition covers the features introduced by the recent IEEE 1800-2012.

System Verilog standard, explaining in detail the new and enhanced assertion constructs. The book makes SVA usable and accessible for hardware designers, verification engineers, formal verification specialists and EDA tool developers. With numerous exercises, ranging in depth and difficulty, the book is also suitable as a text for students.

這本書是一本關於使用System Verilog Assertions (SVA)進行硬體設計的斷言驗證的全面指南。它使讀者能夠通過在模擬測試、覆蓋率收集和形式分析中使用斷言技術來降低驗證成本。該書詳細描述了SVA的所有語言特性，並提供了逐步示例，展示如何使用它們來構建強大且可重用的屬性集。該書還展示了SVA如何融入更廣泛的System Verilog語言，演示了斷言如何與其他System Verilog組件互動。對於新手硬體驗證的讀者，該書提供了描述設計模型和行為性質的一般材料，以及它們如何被激活以及斷言在其中扮演的不同角色。這本第二版涵蓋了最近IEEE 1800-2012 System Verilog標準引入的功能，詳細解釋了新的和增強的斷言結構。該書使SVA對硬體設計師、驗證工程師、形式驗證專家和EDA工具開發人員可用且易於理解。該書還包含了許多深度和難度不同的練習題，也適合作為學生的教材。