CMOS VLSI Layout and Verification of a Simd Computer
Zheng, Jianqing, National Aeronautics and Space Administr
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A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.
