相關主題
商品描述
This is a workbook for Universal Verification Methodology
類似商品
-
VIP 95折
Computer-Aided Verification of Coordinating Processes: The Automata-Theoretic Approach (Princeton Legacy Library)$7,380$7,011 -
VIP 95折
Designing with FPGAs and CPLDs$3,030$2,879 -
VIP 95折
ASIC/SoC Functional Design Verification: A Comprehensive Guide to Technologies and Methodologies (Hardcover)$7,200$6,840 -
VIP 95折
Getting Started with UVM: A Beginner's Guide (Paperback)$1,100$1,045 -
VIP 95折
Optimization of Gridshells Against Instability Considering Joints' Mechanical Performance$1,910$1,815 -
Verification Methodology Manual for SystemVerilog (Hardcover) (書側有霉斑,不介意在下單)$1,380$1,352 -
VIP 95折
Analog-Mixed Signal Verification$2,930$2,784 -
95折
$2,432Visual Data Mining: The VisMiner Approach, 2/e (Hardcover) -
VIP 95折
Writing Testbenches using SystemVerilog (Hardcover)$8,920$8,474 -
VIP 95折
Practical UVM: Step by Step with IEEE 1800.2 (Paperback)$2,500$2,375