Circuit Techniques for Low-Voltage and High-Speed A/d Converters (Hardcover)
Mikko E. Waltari, Kari A.I. Halonen
- 出版商: Kluwer Academic Publ
- 出版日期: 2002-10-31
- 售價: $830
- 貴賓價: 9.8 折 $813
- 語言: 英文
- 頁數: 254
- 裝訂: Hardcover
- ISBN: 1402072449
- ISBN-13: 9781402072444
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商品描述
The increasing digitalization in all spheres of electronics
applications, from telecommunications systems to consumer electronics
appliances, requires analog-to-digital converters (ADCs) with a higher sampling
rate, higher resolution, and lower power consumption. The evolution of
integrated circuit technologies partially helps in meeting these requirements by
providing faster devices and allowing for the realization of more complex
functions in a given silicon area, but simultaneously it brings new challenges,
the most important of which is the decreasing supply voltage. Based on the
switched capacitor (SC) technique, the pipelined architecture has most
successfully exploited the features of CMOS technology in realizing high-speed
high-resolution ADCs. An analysis of the effects of the supply voltage and
technology scaling on SC circuits is carried out, and it shows that benefits can
be expected at least for the next few technology generations. The operational
amplifier is a central building block in SC circuits, and thus a comparison of
the topologies and their low voltage capabilities is presented. It is well-known
that the SC technique in its standard form is not suitable for very low supply
voltages, mainly because of insufficient switch control voltage. Two low-voltage
modifications are investigated: switch bootstrapping and the switched opamp (SO)
technique. Improved circuit structures are proposed for both. Two ADC prototypes
using the SO technique are presented, while bootstrapped switches are utilized
in three other prototypes. An integral part of an ADC is the front-end
sample-and-hold (S/H) circuit. At high signal frequencies its linearity is
predominantly determined by the switches utilized. A review of S/H architectures
is presented, and switch linearization by means of bootstrapping is studied and
applied to two of the prototypes. Another important parameter is sampling clock
jitter, which is analyzed and then minimized with carefully-designed clock
generation and buffering. The throughput of ADCs can be increased by using
parallelism. This is demonstrated on the circuit level with the double-sampling
technique, which is applied to S/H circuits and a pipelined ADC. An analysis of
nonidealities in double-sampling is presented. At the system level parallelism
is utilized in a time-interleaved ADC. The mismatch of parallel signal paths
produces errors, for the elimination of which a timing skew insensitive sampling
circuit and a digital offset calibration are developed. Circuit Techniques for
Low-Voltage and High-Speed A/D Converters presents a total of seven prototypes:
two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling
self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two
pipelined ADCs employing the SO techniques. This monograph will prove to be a
useful reference for both academics and professionals whom are active in the
Analog Circuit Design and Communications field.