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商品描述
Description
CMOS PLLs and VCOs for 4G Wireless is the first book devoted to the subject of CMOS PLL and VCO design for future broadband 4th generation wireless devices. These devices will be handheld-centric, requiring very low power consumption and small footprint. They will be able to work across multiple bands and multiple standards covering WWAN (GSM,WCDMA) ,WLAN(802.11 a/b/g) and WPAN(Bluetooth) with different modulations, channel bandwidths , phase noise requirements ,etc. As such, this book discusses design, modeling and optimization techniques for low power fully integrated broadband PLLs and VCOs in deep submicron CMOS.
First, the PLL and VCO performances are studied in the context of the chosen multi-band multi-standard, radio architecture and the adopted frequency plan. Next a thorough study of the design requirements for broadband PLL/VCO design is conducted together with modeling techniques for noise sources in a PLL and VCO focusing on optimization of integrated phase noise for multi-carrier OFDM 64-QAM type applications. Design examples for multi-standard 802.111a/b/g as well as for GSM/WCDMA are fully described and experimental results from 0.18 micron CMOS test chips have demonstrated the validity of the proposed design and optimization techniques. Equally important the work describes techniques for robust high volume production of RF radios in general and for integrated PLL/VCO design in particular including issues such as supply sensitivity, ground bounce and calibration mechanisms.
CMOS PLLS and VCOs for 4G Wireless will be of interest to graduate students in electrical and computer engineering, design managers and RFIC designers in wireless semiconductor companies.
Written for:
Graduate students in electrical and computer engineering, design managers and RFIC designers in wireless semiconductor companies
商品描述(中文翻譯)
**書籍描述**
《CMOS PLLs and VCOs for 4G Wireless》是第一本專注於未來寬頻第四代無線設備的CMOS相位鎖定迴路(PLL)和壓控振盪器(VCO)設計的書籍。這些設備將以手持設備為中心,要求非常低的功耗和小型化的佈局。它們能夠在多個頻段和多個標準下運作,涵蓋WWAN(GSM、WCDMA)、WLAN(802.11 a/b/g)和WPAN(藍牙),並支持不同的調變、通道帶寬、相位噪聲要求等。因此,本書討論了在深亞微米CMOS中,低功耗全整合寬頻PLL和VCO的設計、建模和優化技術。
首先,PLL和VCO的性能在所選擇的多頻段多標準無線架構及採用的頻率規劃的背景下進行研究。接著,對於寬頻PLL/VCO設計的設計要求進行徹底研究,並針對PLL和VCO中的噪聲源進行建模技術,重點優化多載波OFDM 64-QAM類型應用的整合相位噪聲。針對多標準802.11a/b/g以及GSM/WCDMA的設計範例進行了詳細描述,並且來自0.18微米CMOS測試晶片的實驗結果證明了所提出的設計和優化技術的有效性。同樣重要的是,該研究描述了RF無線電的穩健高產量生產技術,特別是針對整合PLL/VCO設計,包括供電敏感性、接地反彈和校準機制等問題。
《CMOS PLLs and VCOs for 4G Wireless》將吸引電機與計算機工程的研究生、設計經理以及無線半導體公司的RFIC設計師。
