Multi-Core Cache Hierarchies (Paperback)

A key determinant of overall system performance and power dissipation is the cache hierarchy since access to off-chip memory consumes many more cycles and energy than on-chip accesses. In addition, multi-core processors are expected to place ever higher bandwidth demands on the memory system. All these issues make it important to avoid off-chip memory access by improving the efficiency of the on-chip cache. Future multi-core processors will have many large cache banks connected by a network and shared by many cores. Hence, many important problems must be solved: cache resources must be allocated across many cores, data must be placed in cache banks that are near the accessing core, and the most important data must be identified for retention. Finally, difficulties in scaling existing technologies require adapting to and exploiting new technology constraints.

The book attempts a synthesis of recent cache research that has focused on innovations for multi-core processors. It is an excellent starting point for early-stage graduate students, researchers, and practitioners who wish to understand the landscape of recent cache research.

The book is suitable as a reference for advanced computer architecture classes as well as for experienced researchers and VLSI engineers.

Table of Contents: Basic Elements of Large Cache Design / Organizing Data in CMP Last Level Caches / Policies Impacting Cache Hit Rates / Interconnection Networks within Large Caches / Technology / Concluding Remarks

整體系統性能和功耗的關鍵因素是快取層次結構，因為與片上存取相比，對外部記憶體的存取需要更多的週期和能量。此外，多核處理器對記憶體系統的頻寬需求也越來越高。所有這些問題都使得通過提高片上快取的效率來避免對外部記憶體的存取變得重要。未來的多核處理器將通過網絡連接許多大型快取銀行並由多個核心共享。因此，必須解決許多重要的問題：快取資源必須分配給多個核心，數據必須放置在靠近訪問核心的快取銀行中，並且必須識別出最重要的數據以保留。最後，現有技術的擴展困難需要適應和利用新的技術限制。

本書試圖綜合近期針對多核處理器創新的快取研究，對於希望了解最新快取研究領域的初級研究生、研究人員和從業人員來說，是一個很好的起點。

本書適合作為高級計算機架構課程的參考書，同時也適合有經驗的研究人員和VLSI工程師參考。

目錄：大型快取設計的基本要素 / 在CMP最後一級快取中組織數據 / 影響快取命中率的策略 / 大型快取中的互連網絡 / 技術 / 結論