Introduction to Noise-Resilient Computing (Paperback)

S. N. Yanushkevich, S. Kasai, G. Tangim, A. H. Tran, T. Mohamed, V. P. Shmerko


Noise abatement is the key problem of small-scaled circuit design. New computational paradigms are needed -- as these circuits shrink, they become very vulnerable to noise and soft errors. In this lecture, we present a probabilistic computation framework for improving the resiliency of logic gates and circuits under random conditions induced by voltage or current fluctuation. Among many probabilistic techniques for modeling such devices, only a few models satisfy the requirements of efficient hardware implementation -- specifically, Boltzman machines and Markov Random Field (MRF) models. These models have similar built-in noise-immunity characteristics based on feedback mechanisms. In probabilistic models, the values 0 and 1 of logic functions are replaced by degrees of beliefs that these values occur. An appropriate metric for degree of belief is probability. We discuss various approaches for noise-resilient logic gate design, and propose a novel design taxonomy based on implementation of the MRF model by a new type of binary decision diagram (BDD), called a cyclic BDD. In this approach, logic gates and circuits are designed using 2-to-1 bi-directional switches. Such circuits are often modeled using Shannon expansions with the corresponding graph-based implementation, BDDs. Simulation experiments are reported to show the noise immunity of the proposed structures. Audiences who may benefit from this lecture include graduate students taking classes on advanced computing device design, and academic and industrial researchers. Table of Contents: Introduction to probabilistic computation models / Nanoscale circuits and fluctuation problems / Estimators and Metrics / MRF Models of Logic Gates / Neuromorphic models / Noise-tolerance via error correcting / Conclusion and future work


噪音抑制是小型電路設計的關鍵問題。隨著這些電路的縮小,它們變得非常容易受到噪音和軟錯誤的影響,因此需要新的計算範式。在這個講座中,我們提出了一個概率計算框架,用於改善在電壓或電流波動引起的隨機條件下邏輯閘和電路的韌性。在許多用於建模此類設備的概率技術中,只有少數模型滿足高效硬體實現的要求,具體來說,是Boltzman機器和馬爾可夫隨機場(MRF)模型。這些模型具有類似的內建噪音免疫特性,基於反饋機制。在概率模型中,邏輯函數的0和1的值被置換為對這些值發生的信念程度。適當的信念程度度量是概率。我們討論了各種抗噪音邏輯閘設計的方法,並提出了一種基於MRF模型的新型二元決策圖(BDD)的設計分類法,稱為循環BDD。在這種方法中,使用2對1雙向開關來設計邏輯閘和電路。這些電路通常使用Shannon展開和相應的基於圖形的實現方式,即BDDs進行建模。報告了模擬實驗以展示所提結構的抗噪音能力。受益於本講座的觀眾包括修讀高級計算設備設計課程的研究生以及學術和工業研究人員。目錄:概率計算模型介紹 / 納米級電路和波動問題 / 估計器和度量 / 邏輯閘的MRF模型 / 神經形態模型 / 通過錯誤修正實現噪音容忍度 / 結論和未來工作