Introduction to Noise-Resilient Computing (Paperback)
暫譯: 噪聲韌性計算導論 (平裝本)
S. N. Yanushkevich, S. Kasai, G. Tangim, A. H. Tran, T. Mohamed, V. P. Shmerko
- 出版商: Morgan & Claypool
- 出版日期: 2013-01-01
- 售價: $1,400
- 貴賓價: 9.5 折 $1,330
- 語言: 英文
- 頁數: 152
- 裝訂: Paperback
- ISBN: 1627050221
- ISBN-13: 9781627050227
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相關分類:
電力電子 Power-electronics、電子學 Eletronics、電路學 Electric-circuits
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商品描述
Noise abatement is the key problem of small-scaled circuit design. New computational paradigms are needed -- as these circuits shrink, they become very vulnerable to noise and soft errors. In this lecture, we present a probabilistic computation framework for improving the resiliency of logic gates and circuits under random conditions induced by voltage or current fluctuation. Among many probabilistic techniques for modeling such devices, only a few models satisfy the requirements of efficient hardware implementation -- specifically, Boltzman machines and Markov Random Field (MRF) models. These models have similar built-in noise-immunity characteristics based on feedback mechanisms. In probabilistic models, the values 0 and 1 of logic functions are replaced by degrees of beliefs that these values occur. An appropriate metric for degree of belief is probability. We discuss various approaches for noise-resilient logic gate design, and propose a novel design taxonomy based on implementation of the MRF model by a new type of binary decision diagram (BDD), called a cyclic BDD. In this approach, logic gates and circuits are designed using 2-to-1 bi-directional switches. Such circuits are often modeled using Shannon expansions with the corresponding graph-based implementation, BDDs. Simulation experiments are reported to show the noise immunity of the proposed structures. Audiences who may benefit from this lecture include graduate students taking classes on advanced computing device design, and academic and industrial researchers. Table of Contents: Introduction to probabilistic computation models / Nanoscale circuits and fluctuation problems / Estimators and Metrics / MRF Models of Logic Gates / Neuromorphic models / Noise-tolerance via error correcting / Conclusion and future work
商品描述(中文翻譯)
噪音抑制是小型電路設計的關鍵問題。隨著這些電路的縮小,新的計算範式是必要的,因為它們變得非常容易受到噪音和軟錯誤的影響。在這次講座中,我們提出了一個概率計算框架,以提高邏輯閘和電路在由電壓或電流波動引起的隨機條件下的韌性。在許多用於建模這類設備的概率技術中,只有少數模型滿足高效硬體實現的要求,特別是玻爾茲曼機和馬可夫隨機場(MRF)模型。這些模型基於反饋機制具有類似的內建抗噪音特性。在概率模型中,邏輯函數的值0和1被替換為這些值出現的信念程度。信念程度的適當度量是概率。我們討論了各種抗噪音邏輯閘設計的方法,並提出了一種基於通過一種新型二元決策圖(BDD)實現MRF模型的創新設計分類法,稱為循環BDD。在這種方法中,邏輯閘和電路是使用2對1的雙向開關設計的。這類電路通常使用香農展開進行建模,並具有相應的基於圖形的實現,即BDD。報告了模擬實驗以顯示所提結構的抗噪音能力。可能從這次講座中受益的觀眾包括修習先進計算設備設計課程的研究生,以及學術和工業研究人員。目錄:概率計算模型介紹 / 奈米級電路與波動問題 / 估計器與度量 / 邏輯閘的MRF模型 / 類神經模型 / 通過錯誤更正實現抗噪音 / 結論與未來工作