Layout Techniques for MOSFETs

Salvador Pinillos Gimenez

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商品描述

This book aims at describing in detail the different layout techniques for remarkably boosting the electrical performance and the ionizing radiation tolerance of planar Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs) without adding any costs to the current planar Complementary MOS (CMOS) integrated circuits (ICs) manufacturing processes. These innovative layout styles are based on pn junctions engineering between the drain/source and channel regions or simply MOSFET gate layout change. These interesting layout structures are capable of incorporating new effects in the MOSFET structures, such as the Longitudinal Corner Effect (LCE), the Parallel connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), the Deactivation of the Parallel MOSFETs in the Bird's Beak Regions (DEPAMBBRE), and the Drain Leakage Current Reduction Effect (DLECRE), which are still seldom explored by the semiconductor and CMOS ICs industries. Several three-dimensional (3D) numerical simulations and experimental works are referenced in this book to show how these layout techniques can help the designers to reach the analog and digital CMOS ICs specifications with no additional cost. Furthermore, the electrical performance and ionizing radiation robustness of the analog and digital CMOS ICs can significantly be increased by using this gate layout approach.

商品描述(中文翻譯)

本書旨在詳細描述不同的佈局技術,以顯著提升平面金屬氧化物半導體場效應電晶體(MOSFET)的電性能和耐電離輻射能力,而不增加目前平面互補式金屬氧化物半導體(CMOS)集成電路(IC)製造過程的成本。這些創新的佈局風格基於漏極/源極和通道區域之間的pn結工程或僅僅是MOSFET閘極佈局的改變。這些有趣的佈局結構能夠在MOSFET結構中引入新的效應,例如長向角效應(LCE)、不同通道長度的MOSFET並聯效應(PAMDLE)、鳥嘴區域並聯MOSFET的失活效應(DEPAMBBRE)和漏極漏電流減少效應(DLECRE),這些效應在半導體和CMOS IC行業中仍然很少被探索。本書引用了多個三維(3D)數值模擬和實驗作品,以展示這些佈局技術如何幫助設計師在不增加成本的情況下達到模擬和數字CMOS IC的規格要求。此外,通過使用這種閘極佈局方法,模擬和數字CMOS IC的電性能和耐電離輻射能力可以顯著提高。