The Fourth Terminal: Benefits of Body-Biasing Techniques for Fdsoi Circuits and Systems
暫譯: 第四終端：Fdsoi電路與系統的身體偏壓技術優勢

本書討論了集成電路和系統中 Body-Biasing 的優勢和挑戰，以及生成這種 Body-Bias 電壓所需的設計基礎設施的部署。這些新的設計解決方案使最新應用（如物聯網和 5G 通訊）能夠實現最先進的能源效率和系統靈活性。

Sylvain CLERC (M'99) received the Engineering Degree in Digital System Architecture from Grenoble National Polytechnical Institute in 1993. From 1995 to 1999 he was with Dolphin Integration, now Dolphin Design, Meylan, France, working on memory generator design and automated layout. In 1999, he joined STMicroelectronics, Crolles, France, in Technology Design Platform group. He was responsible for standard cell design and Silicon qualification. From 2006 to 2016 he was in a team in charge of radiation hardening and silicon IPs qualification for space and terrestrial environments. He is now working in Digital Design Flow Methodology team. His current research domain is Safety and Energy Efficient circuit design.

Thierry DI GILIO was born in 1978 in Marseille, France. He received his his M.Sc in Physic and Modelling Of complex Systems from University of Provence, France in 2002. In 2006, he obtained his PhD degree in nano-electronic from University of Provence. During 3 years, he worked at Sofradir (Veurey-Voroise, France) as a consultant, and designed several Readout Circuits for cooled infrared detector applications. In 2011 he joined STMicroelectronics Central R&D (in Crolles, France) to design embedded power management circuits for digital and RF SoCs including the development of embedded boby biasing solutions for FDSOI technologies. He is now in charge of Power Management IP design within Imaging Product group.

Andreia Cathelin (M'04, SM'11) is a Technology R&D Fellow at STMicroelectronics, Crolles France. She started electrical engineering studies at the Polytechnic Institute of Bucarest, Romania and graduated with MS from the Institut Supérieur d'Electronique du Nord (ISEN), Lille, France in 1994. In 1998 and 2013 respectively, she received PhD and "habilitation à diriger des recherches" (French highest academic degree) from the Université de Lille 1, France.

Since 1998, she has been with STMicroelectronics, Crolles, France. Her focus areas are in the design of RF/mmW/THz and ultra-low-power circuits and systems. She is leading and driving advanced R&D research topics, also in collaboration with major research teams from Universities worldwide. She is as well one of the pioneers worldwide in FD-SOI CMOS design.

Andreia has had numerous responsibilities inside the IEEE community since more than 10 years. At ISSCC, she has been the RF sub-committee chair from 2012 to 2015, and since 2016 is the Forums Chair and member of the Executive Committee. She has been the ESSCIRC-ESSDERC Steering Committee Chair from 2015 to 2017 and is the Technical Program Chair for ESSCIRC2020. She has served different positions on the Technical Program Committees of VLSI Symposium on Circuits from 2010 till 2016, and is now member of its Executive Committee. She has been an elected member of the IEEE SSCS Adcom for the term January 2015 to December 2017 and for the 2020-2022 term, and is an active member of the IEEE SSCS Women in Circuits group.

Andreia has authored or co-authored 130+ technical papers and 7 book chapters and has filed more than 25 patents. She is a co-recipient of the ISSCC 2012 Jan Van Vessem Award for Outstanding European Paper and of the ISSCC 2013 Jack Kilby Award for Outstanding Student Paper. She is as well the winner of the 2012 STMicroelectronics Technology Council Innovation Prize, for having introduced on the company's roadmap the integrated CMOS THz technology for imaging applications.

Sylvain CLERC (M'99) 於1993年獲得法國格勒諾布爾國立工藝學院的數位系統架構工程學位。從1995年到1999年，他在Dolphin Integration（現為Dolphin Design）工作，專注於記憶體生成器設計和自動佈局。1999年，他加入法國Crolles的STMicroelectronics，成為技術設計平台小組的一員，負責標準單元設計和矽片驗證。從2006年到2016年，他在一個負責輻射抗擾和矽片IP驗證的團隊工作，該團隊專注於太空和地面環境的應用。他目前在數位設計流程方法論團隊工作，研究領域為安全性和能源效率電路設計。

Thierry DI GILIO 於1978年出生於法國馬賽。他於2002年在法國普羅旺斯大學獲得物理與複雜系統建模的碩士學位。2006年，他在普羅旺斯大學獲得納米電子學博士學位。在三年的時間裡，他在Sofradir（法國Veurey-Voroise）擔任顧問，設計了幾個用於冷卻紅外探測器應用的讀出電路。2011年，他加入STMicroelectronics中央研發部（位於法國Crolles），設計數位和RF SoC的嵌入式電源管理電路，包括為FDSOI技術開發嵌入式偏壓解決方案。他目前負責影像產品組的電源管理IP設計。

Andreia Cathelin (M'04, SM'11) 是STMicroelectronics法國Crolles的技術研發研究員。她在羅馬尼亞布加勒斯特的工藝學院開始學習電機工程，並於1994年在法國里爾的北方電子高等學院（ISEN）獲得碩士學位。她於1998年和2013年分別在法國里爾大學獲得博士學位和「指導研究的資格」（法國最高學術學位）。

自1998年以來，她一直在STMicroelectronics法國Crolles工作。她的專注領域包括RF/mmW/THz和超低功耗電路及系統的設計。她領導並推動先進的研發研究主題，並與全球主要大學的研究團隊合作。她也是FD-SOI CMOS設計領域的全球先驅之一。

Andreia在IEEE社群內擔任了超過10年的多項職務。在ISSCC中，她於2012年至2015年擔任RF小組委員會主席，自2016年起擔任論壇主席及執行委員會成員。她於2015年至2017年擔任ESSCIRC-ESSDERC指導委員會主席，並擔任ESSCIRC2020的技術計畫主席。她在2010年至2016年間擔任VLSI Symposium on Circuits技術計畫委員會的不同職位，現在是其執行委員會成員。她曾於2015年1月至2017年12月及2020年至2022年任期內當選IEEE SSCS Adcom成員，並且是IEEE SSCS Women in Circuits小組的活躍成員。

Andreia已發表或共同發表超過130篇技術論文和7章書籍，並申請了超過25項專利。她是2012年ISSCC Jan Van Vessem獎的共同獲獎者，該獎項表彰優秀的歐洲論文，以及2013年ISSCC Jack Kilby獎的優秀學生論文獲獎者。她還是2012年STMicroelectronics技術委員會創新獎的得主，因為她在公司的路線圖中引入了用於影像應用的集成CMOS THz技術。